4.2.134 DCGCSSI Register (Offset = 0x81C) [reset = 0x0]
Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI)
The DCGCSSI register lets software enable and disable the SSI modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
NOTE
This register controls the clocking for the SSI modules.
DCGCSSI is shown in Figure 4-140 and described in Table 4-147.
Return to Summary Table.
Figure 4-140 DCGCSSI Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
D3 |
D2 |
D1 |
D0 |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 4-147 DCGCSSI Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-4 |
RESERVED |
R |
0x0 |
|
| 3 |
D3 |
R/W |
0x0 |
SSI Module 3 Deep-Sleep Mode Clock Gating Control
0x0 = SSI module 3 is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to SSI module 3 in deep-sleep mode.
|
| 2 |
D2 |
R/W |
0x0 |
SSI Module 2 Deep-Sleep Mode Clock Gating Control
0x0 = SSI module 2 is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to SSI module 2 in deep-sleep mode.
|
| 1 |
D1 |
R/W |
0x0 |
SSI Module 1 Deep-Sleep Mode Clock Gating Control
0x0 = SSI module 1 is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to SSI module 1 in deep-sleep mode.
|
| 0 |
D0 |
R/W |
0x0 |
SSI Module 0 Deep-Sleep Mode Clock Gating Control
0x0 = SSI module 0 is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to SSI module 0 in deep-sleep mode.
|