4.2.133 DCGCUART Register (Offset = 0x818) [reset = 0x00]
Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control (DCGCUART)
The DCGCUART register lets software enable and disable the UART modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to save power.
NOTE
This register controls the clocking for the UART modules.
DCGCUART is shown in Figure 4-139 and described in Table 4-146.
Return to Summary Table.
Figure 4-139 DCGCUART Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
D7 |
D6 |
D5 |
D4 |
D3 |
D2 |
D1 |
D0 |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 4-146 DCGCUART Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-8 |
RESERVED |
R |
0x0 |
|
| 7 |
D7 |
R/W |
0x0 |
UART Module 7 Deep-Sleep Mode Clock Gating Control
0x0 = UART module 7 is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to UART module 7 in deep-sleep mode.
|
| 6 |
D6 |
R/W |
0x0 |
UART Module 6 Deep-Sleep Mode Clock Gating Control
0x0 = UART module 6 is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to UART module 6 in deep-sleep mode.
|
| 5 |
D5 |
R/W |
0x0 |
UART Module 5 Deep-Sleep Mode Clock Gating Control
0x0 = UART module 5 is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to UART module 5 in deep-sleep mode.
|
| 4 |
D4 |
R/W |
0x0 |
UART Module 4 Deep-Sleep Mode Clock Gating Control
0x0 = UART module 4 is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to UART module 4 in deep-sleep mode.
|
| 3 |
D3 |
R/W |
0x0 |
UART Module 3 Deep-Sleep Mode Clock Gating Control
0x0 = UART module 3 is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to UART module 3 in deep-sleep mode.
|
| 2 |
D2 |
R/W |
0x0 |
UART Module 2 Deep-Sleep Mode Clock Gating Control
0x0 = UART module 2 is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to UART module 2 in deep-sleep mode.
|
| 1 |
D1 |
R/W |
0x0 |
UART Module 1 Deep-Sleep Mode Clock Gating Control
0x0 = UART module 1 is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to UART module 1 in deep-sleep mode.
|
| 0 |
D0 |
R/W |
0x0 |
UART Module 0 Deep-Sleep Mode Clock Gating Control
0x0 = UART module 0 is disabled in deep-sleep mode.
0x1 = Enable and provide a clock to UART module 0 in deep-sleep mode.
|