14.8.3 DES_DMAMIS Register (Offset = 0x38) [reset = 0x0]
DES DMA Masked Interrupt Status (DES_DMAMIS)
The DES DMA Masked Interrupt Status register displays the raw interrupts that are unmasked in the DES DMA Raw Interrupt Status (DES_DMARIS) register.
DES_DMAMIS is shown in Figure 14-23 and described in Table 14-27.
Return to Summary Table.
Figure 14-23 DES_DMAMIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DOUT |
DIN |
CIN |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 14-27 DES_DMAMIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-3 |
RESERVED |
R |
0x0 |
|
| 2 |
DOUT |
R |
0x0 |
Data Out DMA Done Masked Interrupt Status
0x0 = An interrupt has not occurred or is masked.
0x1 = A DOUT interrupt has occurred.
|
| 1 |
DIN |
R |
0x0 |
Data In DMA Done Masked Interrupt Status
0x0 = An interrupt has not occurred or is masked.
0x1 = A DIN interrupt has occurred.
|
| 0 |
CIN |
R |
0x0 |
Context In DMA Done Raw Interrupt Status
0x0 = An interrupt has not occurred or is masked.
0x1 = A CIN interrupt has occurred.
|