14.8.2 DES_DMARIS Register (Offset = 0x34) [reset = 0x0]
DES DMA Raw Interrupt Status (DES_DMARIS)
The DES DMA Raw Interrupt Status register contains the raw interrupt status. If any of these bits read 1, the processor is interrupted if the corresponding masked interrupt status bit is set to 1.
DES_DMARIS is shown in Figure 14-22 and described in Table 14-26.
Return to Summary Table.
Figure 14-22 DES_DMARIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DOUT |
DIN |
CIN |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 14-26 DES_DMARIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-3 |
RESERVED |
R |
0x0 |
|
| 2 |
DOUT |
R/W |
0x0 |
Data Out DMA Done Raw Interrupt Status
0x0 = No Interrupt.
0x1 = The µDMA has written the last word of the process result and an interrupt has been triggered and is pending.
|
| 1 |
DIN |
R/W |
0x0 |
Data In DMA Done Raw Interrupt Status
0x0 = No Interrupt.
0x1 = The µDMA has written the last word of input data to the internal FIFO of the engine and an interrupt has been triggered and is pending.
|
| 0 |
CIN |
R/W |
0x0 |
Context In DMA Done Raw Interrupt Status
0x0 = No interrupt.
0x1 = The µDMA has completed a context write to the internal register and an interrupt has been triggered and is pending.
|