15.3.3.8 DMA Interrupts

Interrupts can be generated as a result of various transfer events. The current status of interrupts can be read from the EMACDMARIS register and are enabled to trigger an interrupt through the programming of the Ethernet MAC DMA Interrupt Mask (EMACDMAIM) register. There are two groups of transfer event interrupts: Normal and Abnormal. The following lists the two groups:

• Normal Interrupts:
  • Transmit Interrupt (TI, bit 0): Indicates that frame transmission is complete.
  • Transmit Buffer Unavailable (TU, bit 2): Indicates the CPU owns the next descriptor in the transmit list and the DMA cannot acquire it.
  • Receive Interrupt (RI, bit 6): Indicates the frame reception is complete.
  • Early Receive Interrupt (ERI, bit 14): Indicates the DMA has filled the first half of the data buffer of the packet
• Abnormal Interrupts:
  • Transmit Process Stopped (TPS, bit 1): Indicates transmission is stopped.
  • Transmit Jabber Timeout (TJT, bit 3): Indicates the Transmit Jabber Timer expired.
  • Receive FIFO Overflow (OVF, bit 4): Indicates the receive buffer had an overflow during frame reception.
  • Transmit Underflow (UNF, bit 5): Indicates the transmit buffer had an underflow during frame transmission.
  • Receive Buffer Unavailable (RU, bit): Indicates the CPU owns the next descriptor in the receive list and the DMA cannot acquire it.
  • Receive Process Stopped (RPS, bit 8): Indicates the receive process entered the STOP state.
  • Receive Watchdog Timeout (RWT, bit 9): Indicates a frame length greater than 2KB is received (10240 when Jumbo Frame is enabled).
  • Early Transmit Interrupt (ETI, bit 10): Indicates a frame to be transmitted is fully transferred to the TX FIFO.
  • Fatal Bus Error (FBI, bit 13): Indicates a bus error occurred.

Any of the interrupts in the Normal Interrupt group that are enabled in the EMACDMAIM register are ORed together to create the Normal Interrupt Summary (NIS) bit in the EMACDMARIS register. Any of the interrupts in the Abnormal Interrupt group that are enabled in the EMACDMAIM register are ORed together to create the Abnormal Interrupt Summary (AIS) bit in the EMACDMARIS register. Interrupts are cleared by writing a 1 to the corresponding bit position in the EMACDMARIS register. When all enabled interrupts within a group are cleared, the corresponding summary bit is cleared.

Interrupts are not queued and if the interrupt event occurs again before the driver has responded to it, no additional interrupts are generated. An interrupt is only generated once for simultaneous, multiple events. The driver must read the EMACDMARIS register for the cause of the interrupt.

The Ethernet MAC Receive Interrupt Watchdog Timer (EMACRXINTWDT) register, offset 0xC24 can be used to control the Receive Interrupt (RI) assertion. If the RDES1[31] bit (Receive Interrupt) bit has not been set in the receive descriptor and the EMACRXINTWDT register is programmed with a non-zero value, it gets activated as soon as the RX DMA completes a transfer of a received frame to system memory without asserting the receive interrupt. When this counter runs out as per the programmed value, the RI bit is set in the EMACDMARIS register and the interrupt is asserted if the corresponding RI bit is enabled in the EMACDMAIM register. This counter gets disabled before it runs out if a frame is transferred to memory and the RI bit is set because it is enabled for that descriptor.