SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The UART provides an interface to the μDMA controller with separate channels for transmit and receive. The DMA operation of the UART is enabled through the UART DMA Control (UARTDMACTL) register. When DMA operation is enabled, the UART asserts a DMA request on the receive or transmit channel when the associated FIFO can transfer data.
For the receive channel, a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer request is asserted whenever the amount of data in the receive FIFO is at or above the FIFO trigger level configured in the UARTIFLS register.
For the transmit channel, a single transfer request is asserted whenever there is at least one empty location in the transmit FIFO. The burst request is asserted whenever the transmit FIFO contains fewer characters than the FIFO trigger level. The single and burst DMA transfer requests are handled automatically by the μDMA controller depending on how the DMA channel is configured.
NOTE
When using SIR mode (see Section 26.3.4), transfers can be done only in single transfer mode. To ensure single transfer mode, clear the respective SETn bit DMAUSEBURSTSET register for the μDMA channel that is mapped to the UART.
To enable DMA operation for the receive channel, set the RXDMAE bit of the DMA Control (UARTDMACTL) register. To enable DMA operation for the transmit channel, set the TXDMAE bit of the UARTDMACTL register. The UART can also be configured to stop using DMA for the receive channel if a receive error occurs. If the DMAERR bit of the UARTDMACR register is set and a receive error occurs, the DMA receive requests are automatically disabled. This error condition can be cleared by clearing the appropriate UART error interrupt.
When the µDMA is finished transferring data to the TX FIFO or from the RX FIFO, a dma_done signal is sent to the UART to indicate completion. The dma_done status is indicated through the DMATXRIS and DMARXIS bits of the UARTRIS register. An interrupt can be generated from these status bits by setting the DMATXIM and DMARXIM bits in the UARTIM register.
NOTE
The DMATXRIS bit can be used to indicate the completion of data transfer from the µDMA to the TX FIFO. To indicate transfer completion from the serializer of the UART, the EOT bit should be enabled in the UARTCTL register. An interrupt can be generated on an EOT completion by setting the EOTIM bit of the UARTIM register.
See Section 8 for more details about programming the μDMA controller.