SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
DMA may be used to increase efficiency by allowing each sample sequencer to operate independently and transfer data without processor intervention or reconfiguration.
The ADC asserts single and burst µDMA request signals (dma_sreq and dma_req) to the µDMA controller based on the FIFO level. The dma_req signal is generated when the FIFO in question is half-full (that is, at 4 samples for SS0, 2 samples for SS1 and SS2, and at 1 sample for SS3). If, for example, the ADCSSCTL0 register has six samples to transfer, a burst of four values occurs followed by two single transfers (dma_sreq). The dma_done signals (one per sample sequencer) are sent to the ADC to allow for a triggering of DMAINRn interrupt bits in the ADCRIS register. The µDMA is enabled for a specific sample sequencer by setting the appropriate ADENn bit in the ADCACTSS register at offset 0x000.
To use the µDMA with the ADC module, the application must enable the ADC channel through DMA Channel Map Select n (DMACHMAPn) register in the µDMA.
See the Section 8 for more details about programming the µDMA controller.