SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
DMA Channel Control Word (DMACHCTL)
DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure and is used to specify parameters of a µDMA transfer.
NOTE
The offset specified is from the base address of the control structure in system memory, not the µDMA module base address.
DMACHCTL is shown in Figure 8-9 and described in Table 8-16.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DSTINC | DSTSIZE | SRCINC | SRCSIZE | ||||
| R/W-X | R/W-X | R/W-X | R/W-X | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | DSTPROT0 | RESERVED | SRCPROT0 | ARBSIZE | |||
| R-0h | R/W-0h | R-X | R/W-0h | R/W-X | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ARBSIZE | XFERSIZE | ||||||
| R/W-X | R/W-X | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| XFERSIZE | NXTUSEBURST | XFERMODE | |||||
| R/W-X | R/W-X | R/W-X | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | DSTINC | R/W | X | Destination Address Increment
This field configures the destination address increment. The address increment value must be equal or greater than the value of the destination size (DSTSIZE). 0x0 = Byte; Increment by 8-bit locations 0x1 = Half-word; Increment by 16-bit locations 0x2 = Word; Increment by 32-bit locations 0x3 = No increment. Address remains set to the value of the Destination Address End Pointer (DMADSTENDP) for the channel. |
| 29-28 | DSTSIZE | R/W | X | Destination Data Size
This field configures the destination item data size. DSTSIZE must be the same as SRCSIZE. 0x0 = Byte; 8-bit data size 0x1 = Half-word; 16-bit data size 0x2 = Word; 32-bit data size 0x3 = Reserved |
| 27-26 | SRCINC | R/W | X | Source Address Increment
This field configures the source address increment. The address increment value must be equal or greater than the value of the source size (SRCSIZE). 0x0 = Byte; Increment by 8-bit locations 0x1 = Half-word; Increment by 16-bit locations 0x2 = Word; Increment by 32-bit locations 0x3 = No increment
|
| 25-24 | SRCSIZE | R/W | X | Source Data Size
This field configures the source item data size. DSTSIZE must be the same as SRCSIZE. 0x0 = Byte; 8-bit data size. 0x1 = Half-word; 16-bit data size. 0x2 = Word; 32-bit data size. 0x3 = Reserved |
| 23-22 | RESERVED | R | 0x0 |
|
| 21 | DSTPROT0 | R/W | 0x0 | Destination Privilege Access
This bit controls the privilege access protection for destination data writes. For AES, DES, or SHA accesses, this bit must be set to 1. 0 = The access is nonprivileged. 1 = The access is privileged. |
| 20-19 | RESERVED | R | X |
|
| 18 | SRCPROT0 | R/W | 0x0 | Source Privilege Access
This bit controls the privilege access protection for source data reads. For AES, DES, or SHA accesses, this bit must be set to 1. 0 = The access is nonprivileged. 1 = The access is privileged. |
| 17-14 | ARBSIZE | R/W | X | Arbitration Size
This field configures the number of transfers that can occur before the µDMA controller re-arbitrates. The possible arbitration rate configurations represent powers of 2 and are shown below. 0x0 = 1 TransferArbitrates after each µDMA transfer 0x1 = 2 Transfers 0x2 = 4 Transfers 0x3 = 8 Transfers 0x4 = 16 Transfers 0x5 = 32 Transfers 0x6 = 64 Transfers 0x7 = 128 Transfers 0x8 = 256 Transfers 0x9 = 512 Transfers 0xA-0xF = 1024 Transfers. In this configuration, no arbitration occurs during the µDMA transfer because the maximum transfer size is 1024. |
| 13-4 | XFERSIZE | R/W | X | Transfer Size (minus 1)
This field configures the total number of items to transfer. The value of this field is 1 less than the number to transfer (value 0 means transfer 1 item). The maximum value for this 10-bit field is 1023 which represents a transfer size of 1024 items. The transfer size is the number of items, not the number of bytes. If the data size is 32 bits, then this value is the number of 32-bit words to transfer. The µDMA controller updates this field immediately before entering the arbitration process, so it contains the number of outstanding items that is necessary to complete the µDMA cycle. |
| 3 | NXTUSEBURST | R/W | X | Next Useburst
This field controls whether the Useburst SET[n] bit is automatically set for the last transfer of a peripheral scatter-gather operation. Normally, for the last transfer, if the number of remaining items to transfer is less than the arbitration size, the µDMA controller uses single transfers to complete the transaction. If this bit is set, then the controller uses a burst transfer to complete the last transfer. |
| 2-0 | XFERMODE | R/W | X | µDMA Transfer Mode
This field configures the operating mode of the µDMA cycle. See Table 8-17 for a detailed explanation of transfer modes. Because this register is in system RAM, it has no reset value. Therefore, this field should be initialized to 0 before the channel is enabled. 0x0 = Stop 0x1 = Basic 0x2 = Auto-Request 0x3 = Ping-Pong 0x4 = Memory Scatter-Gather 0x5 = Alternate Memory Scatter-Gather 0x6 = Peripheral Scatter-Gather 0x7 = Alternate Peripheral Scatter-Gather |
| Mode | Description |
|---|---|
| Stop | Channel is stopped or configuration data is invalid. No more transfers can occur. |
| Basic | For each trigger (whether from a peripheral or a software request), the µDMA controller performs the number of transfers specified by the ARBSIZE field. |
| Auto-Request | The initial request (software- or peripheral-initiated) is sufficient to complete the entire transfer of XFERSIZE items without any further requests. |
| Ping-Pong | This mode uses both the primary and alternate control structures for this channel. When the number of transfers specified by the XFERSIZE field have completed for the current control structure (primary or alternate), the µDMA controller switches to the other one. These switches continue until one of the control structures is not set to ping-pong mode. At that point, the µDMA controller stops. An interrupt is generated on completion of the transfers configured by each control structure. See Section 8.3.5.4. |
| Memory Scatter-Gather | When using this mode, the primary control structure for the channel is configured to allow a list of operations (tasks) to be performed. The source address pointer specifies the start of a table of tasks to be copied to the alternate control structure for this channel. The XFERMODE field for the alternate control structure should be configured to 0x5 (Alternate memory scatter-gather) to perform the task. When the task completes, the µDMA switches back to the primary channel control structure, which then copies the next task to the alternate control structure. This process continues until the table of tasks is empty. The last task must have an XFERMODE value other than 0x5. Note that for continuous operation, the last task can update the primary channel control structure back to the start of the list or to another list. See Section 8.3.5.5. |
| Alternate Memory Scatter-Gather | This value must be used in the alternate channel control data structure when the µDMA controller operates in Memory Scatter-Gather mode. |
| Peripheral Scatter-Gather | This value must be used in the primary channel control data structure when the µDMA controller operates in Peripheral Scatter-Gather mode. In this mode, the µDMA controller operates exactly the same as in Memory Scatter-Gather mode, except that instead of performing the number of transfers specified by the XFERSIZE field in the alternate control structure at one time, the µDMA controller only performs the number of transfers specified by the ARBSIZE field per trigger; see Basic mode for details. See Section 8.3.5.6. |
| Alternate Peripheral Scatter-Gather | This value must be used in the alternate channel control data structure when the µDMA controller operates in Peripheral Scatter-Gather mode. |