8.6.18 DMACHMAP0 Register (Offset = 0x510) [reset = 0x0]
DMA Channel Map Select 0 (DMACHMAP0)
Each 4-bit field of the DMACHMAP0 register configures the µDMA channel assignment as specified in .
DMACHMAP0 is shown in Figure 8-27 and described in Table 8-37.
Return to Summary Table.
Figure 8-27 DMACHMAP0 Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| CH7SEL |
CH6SEL |
CH5SEL |
CH4SEL |
| R/W-0h |
R/W-0h |
R/W-0h |
R/W-0h |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| CH3SEL |
CH2SEL |
CH1SEL |
CH0SEL |
| R/W-0h |
R/W-0h |
R/W-0h |
R/W-0h |
|
Table 8-37 DMACHMAP0 Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-28 |
CH7SEL |
R/W |
0x0 |
µDMA Channel 7 Source Select
See for channel assignments.
|
| 27-24 |
CH6SEL |
R/W |
0x0 |
µDMA Channel 6 Source Select
See for channel assignments.
|
| 23-20 |
CH5SEL |
R/W |
0x0 |
µDMA Channel 5 Source Select
See for channel assignments.
|
| 19-16 |
CH4SEL |
R/W |
0x0 |
µDMA Channel 4 Source Select
See for channel assignments.
|
| 15-12 |
CH3SEL |
R/W |
0x0 |
µDMA Channel 3 Source Select
See for channel assignments.
|
| 11-8 |
CH2SEL |
R/W |
0x0 |
µDMA Channel 2 Source Select
See for channel assignments.
|
| 7-4 |
CH1SEL |
R/W |
0x0 |
µDMA Channel 1 Source Select
See for channel assignments.
|
| 3-0 |
CH0SEL |
R/W |
0x0 |
µDMA Channel 0 Source Select
See for channel assignments.
|