SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
DMA Channel Control Base Pointer (DMACTLBASE)
The DMACTLBASE register must be configured so that the base pointer points to a location in system memory.
The amount of system memory that must be assigned to the µDMA controller depends on the number of µDMA channels used and whether the alternate channel control data structure is used. See Section 8.3.4 for details about the Channel Control Table. The base address must be aligned on a 1024-byte boundary. This register cannot be read when the µDMA controller is in the reset state.
DMACTLBASE is shown in Figure 8-12 and described in Table 8-22.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR | RESERVED | ||||||||||||||||||||||||||||||
| R/W-0h | R-0h | ||||||||||||||||||||||||||||||