SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
DMA Channel Enable Clear (DMAENACLR)
Each bit of the DMAENACLR register represents the corresponding µDMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAENASET register.
DMAENACLR is shown in Figure 8-21 and described in Table 8-31.
Return to Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR[n] | |||||||||||||||||||||||||||||||
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