SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
DMA Channel Wait-on-Request Status (DMAWAITSTAT)
This read-only register indicates that the µDMA channel is waiting on a request. A peripheral can hold off the µDMA from performing a single request until the peripheral is ready for a burst request to enhance the µDMA performance. The use of this feature is dependent on the design of the peripheral and is not controllable by software in any way. This register cannot be read when the µDMA controller is in the reset state.
DMAWAITSTAT is shown in Figure 8-14 and described in Table 8-24.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WAITREQ[n] | |||||||||||||||||||||||||||||||
R-03C3CF00h | |||||||||||||||||||||||||||||||