SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Deep-Sleep Power Configuration (DSLPPWRCFG)
This register provides configuration information for the power control of the SRAM and flash memory while in deep-sleep mode.
DSLPPWRCFG is shown in Figure 4-29 and described in Table 4-35.
Return to Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | LDOSM | TSPD | |||||
R-0x0 | R/W-0x0 | R/W-0x0 | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FLASHPM | RESERVED | SRAMPM | ||||
R-0x0 | R/W-0x0 | R-0x0 | R/W-0x0 | ||||