4.1.6.4 Dynamic Power Management
In addition to the sleep and deep-sleep modes and the clock gating for the on-chip modules, other power mode options let the LDO, flash memory, and SRAM enter different levels of power savings while in sleep or deep-sleep mode. In addition, software can control the LDO settings to gain a power advantage when running at slower speeds. These features may not be available on all devices; the System Properties (SYSPROP) register provides information on whether a mode is supported on a given MCU. The following registers provide these capabilities:
- Peripheral Power Control (PCx): Controls power to peripheral if that peripheral has the ability to respond to a power request
- Peripheral Memory Power Control (xMPC): Provides power control to some the peripheral memory arrays
- LDO Sleep Power Control (LDOSPCTL): Controls the LDO value in sleep mode
- LDO Deep-Sleep Power Control (LDODPCTL): Controls the LDO value in deep-sleep mode
- LDO Sleep Power Calibration (LDOSPCAL): Provides factory recommendations for the LDO value in sleep mode
- LDO Deep-Sleep Power Calibration (LDODPCAL): Provides factory recommendations for the LDO value in deep-sleep mode
- Sleep Power Configuration (SLPPWRCFG): Controls the power-saving modes for flash memory and SRAM in sleep mode
- Deep-Sleep Power Configuration (DSLPPWRCFG): Controls the power-saving modes for flash memory and SRAM in deep-sleep mode
- Deep-Sleep Clock Configuration (DSCLKCFG): Controls the clocking in deep-sleep mode
- Sleep / Deep-Sleep Power Mode Status (SDPMST): Provides status information on the various power saving events