SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The EEINT register is used to control whether an interrupt should be generated when a write to EEPROM completes as indicated by the EEDONE register value changing from 0x1 to any other value. If the INT bit in this register is set, the ERIS bit in the Flash Controller Raw Interrupt Status (FCRIS) register is set whenever the EEDONE register value changes from 0x1 as the Flash memory and the EEPROM share an interrupt vector.
EEINT is shown in Figure 7-35 and described in Table 7-36.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0x0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||
R-0x0 | R/W-0x0 | ||||||||||||||