15.6.22 EMACADDR3H Register (Offset = 0x58) [reset = 0xFFFF]
Ethernet MAC Address 3 High (EMACADDR3H)
The Ethernet MAC Address 3 High (EMACADDR3H) register holds the upper 16 bits of the fourth 6-byte MAC address of the station.
EMACADDR3H is shown in Figure 15-37 and described in Table 15-46.
Return to Summary Table.
Figure 15-37 EMACADDR3H Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| AE |
SA |
MBC |
RESERVED |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| ADDRHI |
| R/W-0xFFFF |
|
Table 15-46 EMACADDR3H Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31 |
AE |
R/W |
0x0 |
Address Enable.
0x0 = The address filter module ignores the third address for filtering.
0x1 = The address filter module uses the third address for perfect filtering.
|
| 30 |
SA |
R/W |
0x0 |
Source Address.
0x0 = When this bit is reset, the MAC Address3[47:0] is used to compare with the DA fields of the received frame.
0x1 = When this bit is set, the MAC Address3[47:0] is used to compare with the SA fields of the received frame.
|
| 29-24 |
MBC |
R/W |
0x0 |
Mask Byte Control. Mask control bits are provided for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows:
Bit 29: ADDRHI [15:8] of EMACADDR3H register
Bit 28: ADDRHI [7:0] of EMACADDR3H register
Bit 27: ADDRLO [31:24] of EMACADDR3L register
Bit 26: ADDRLO [23:16] of EMACADDR3L register
Bit 25: ADDRLO [15:8] of EMACADDR3L register
Bit 24: ADDRLO [7:0] of EMACADDR3L register
A group of addresses (known as group address filtering) can be filtered by masking one or more bytes of the address.
|
| 23-16 |
RESERVED |
R |
0x0 |
|
| 15-0 |
ADDRHI |
R/W |
0xFFFF |
MAC Address3 [47:32]. This field contains the upper 16 bits [47:32] of the fourth 6-byte MAC address.
|