15.6.70 EMACCC Register (Offset = 0xFC8) [reset = 0x0]
Ethernet MAC Clock Configuration Register (EMACCC)
The following register is used to configure the clocks of the Ethernet Controller.
EMACCC is shown in Figure 15-85 and described in Table 15-95.
Return to Summary Table.
Figure 15-85 EMACCC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
PTPCEN |
POL |
CLKEN |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
| R-0x0 |
|
Table 15-95 EMACCC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-19 |
RESERVED |
R |
0x0 |
|
| 18 |
PTPCEN |
R/W |
0x0 |
PTP Clock Reference Enable. The PTP clock reference is MOSC. This bit enables the MOSC to drive the PTP clock reference of the Ethernet MAC.
0x0 = PTP clock reference is disabled.
0x1 = PTP clock reference is enabled.
|
| 17 |
POL |
R/W |
0x0 |
LED Polarity Control. This bit controls the polarity of the LED outputs coming from the Ethernet PHY.
0x0 = LEDs are active high.
0x1 = LEDs are active low.
|
| 16 |
CLKEN |
R/W |
0x0 |
EN0RREF_CLK Signal Enable. When using the RMII interface, this bit must be set to a 1.
0x0 = EN0RREF_CLK signal is disabled
0x1 = EN0RREF_CLK signal is enabled
|
| 15-0 |
RESERVED |
R |
0x0 |
|