Source Address Insertion or Replacement Control. Bit 30 specifies whether MAC address 0 or 1 registers are used during insertion or replacement for all transmitted frames. Thus for encodings 0x2-0x3, where the most significant bit is 0, the Ethernet MAC Address 0 registers are used. For encodings 0x6-0x7, the Ethernet MAC Address 1 registers are used. Bits [29:28] indicate insertion or replacement. If the value is 0x2 insertion is indicated and if the value is 0x3 replacement is indicated. Changes in this field take effect only on the start of a frame. If a write of this field occurs while a frame is being transmitted, only the subsequent frame can use the updated value, and the current frame does not.

0x0 = Reserved

0x1 = Reserved

0x2 = The Ethernet MAC inserts the content of the Ethernet MAC Address 0 (EMACADDR0x) registers in the SA field of all transmitted frames.

0x3 = The Ethernet MAC replaces the content of the Ethernet MAC Address 0 (EMACADDR0x) registers in the SA field of all transmitted frames.

0x4 = Reserved

0x5 = Reserved

0x6 = The MAC inserts the content of the Ethernet MAC Address 1 (EMACADDR1x) registers in the source address (SA) field for all transmitted frames.

0x7 = The MAC replaces the content of the Ethernet MAC Address 1(EMACADDR1x) registers in the source address (SA) field for all transmitted frames.

IEEE 802.3as Support for 2K Packets. When set, the MAC considers all frames, up to 2,000 bytes in length, as normal packets. This bit is only valid when the JFEN bit is set to 0. When JFEN is set, configuring TWOKPEN has no effect on Giant Frame status.

0x0 = If the JFEN bit is clear, the MAC considers all received frames larger than 1,518 bytes (1522 byes tagged) as Giant Frames.

0x1 = Frames up to 2 KB are considered normal packets.If the JFEN bit is clear, the MAC considers all received frames larger that 2K bytes as Giant frames.

CRC Stripping for Type Frames. When set, the last four bytes (Frame Check Sequence FCS) of all frames of Ether type ((Length/Type field greater than or equal to 0x0600) are removed before forwarding the frame to the application.

0x0 = No bytes are removed.

0x1 = The last four bytes are removed before forwarding.

Watchdog Disable. When this bit is set, the MAC disables the internal watchdog counter on the receiver. The MAC can receive frames of up to 16,384 bytes. When this bit is cleared, the MAC does not allow more than 2,048 bytes (10,240 if JFEN is set to 1) of the frame being received. The MAC cuts off any bytes received after 2,048 bytes.

0x0 = Watchdog counter enabled.

0x1 = Watchdog counter disabled.

Jabber Disable. When this bit is set, the MAC disables the jabber counter on the transmitter. The MAC can transfer frames of up to 16,384 bytes. When this bit is clear, the MAC stops transmission if the application sends out more than 2,048 bytes of data (10,240 if JFEN is set to 1).

0x0 = Jabber counter enabled.

0x1 = Jabber counter disabled.

Jumbo Frame Enable. When this bit is set, the MAC allows jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status.

0x0 = Jumbo frames create giant frame error.

0x1 = Jumbo frames allowed without error.

Inter-Frame Gap (IFG). These bits control the minimum IFG between frames during transmission. In half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 0x4). Lower values are not considered.

0x0 = 96 bit times

0x1 = 88 bit times

0x2 = 80 bit times

0x3 = 72 bit times

0x4 = 64 bit times

0x5 = 56 bit times

0x6 = 48 bit times

0x7 = 40 bit times

Disable Carrier Sense During Transmission. When this bit is set, the MAC transmit module ignores carrier sense in half-duplex mode. Thus, errors are not generated when there is a loss of carrier or no carrier during transmission. When this bit is clear, the MAC transmitter generates errors because of carrier sense and can even abort the transmissions.

0x0 = Generate errors for carrier sense errors.

0x1 = Ignore carrier sense errors.

Port Select. This bit indicates that a 10/100 Mbps interface is supported on this device. This is a read-only bit.

Speed. This bit indicates the speed of the interface.

0x0 = 10 Mbps

0x1 = 100 Mbps

Disable Receive Own. When this bit is set, the MAC disables the reception of frames while transmitting in half-duplex mode. When this bit is clear, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in full-duplex mode.

0x0 = All packets are received by MAC.

0x1 = Disable reception of frames.

Loopback Mode. When this bit is set, the MAC operates in the loopback mode at the MII. The MII Receive clock input, EN0RXCK, is required for the loopback to work properly, because the Transmit clock is not looped-back internally.

0x0 = MAC does not operate in loopback mode.

0x1 = MAC operates in loopback mode.

Duplex Mode. When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously.

0x0 = MAC does not operate in full-duplex mode.

0x1 = MAC operates in full-duplex mode.

Checksum Offload.

0x0 = The checksum offload function in the receiver is disabled and the corresponding PCE and IP HCE status bits in the frame status are always cleared.

0x1 = Checksum Offload EnableSetting this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking.

Disable Retry. When this bit is set, the MAC attempts only one transmission. When a collision occurs on the MII interface, the MAC ignores the current frame transmission and reports a frame abort with excessive collision error in the transmit frame status. When this bit is cleared, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is only applicable in half-duplex mode.

0x0 = MAC retries transmissions based on BL bit field.

0x1 = Only one transmission is attempted by the MAC.

Automatic Pad or CRC Stripping. When this bit is set, the MAC strips the Pad or Frame Check Sequence (FCS) field on the incoming frames only if the value of the length field is less than 1,536 bytes. All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is cleared, the MAC passes all incoming frames, without modifying them, to the Host.

0x0 = All frames are passed to host unmodified.

0x1 = MAC strips FCS field if value of length field is less than 1,536 bytes.

Back-Off Limit. The Back-Off limit determines the random integer number (r) of slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. The random integer r takes the value in the range 0 <= r < 2^k The value of k is programmed in the encodings below and is dependent on the retransmission attempt number, n. This bit is applicable only in the half-duplex mode.

0x0 = k= min (n,10), where k is the lowest value when evaluating n or 10.

0x1 = k= min (n,8), where k is the lowest value when evaluating n or 8.

0x2 = k= min (n,4), where k is the lowest value when evaluating n or 4.

0x3 = k= min (n,1), where k is the lowest value when evaluating n or 1.

Deferral Check. When this bit is set, the deferral check function is enabled in the MAC. When the transmit state machine is deferred for more than 24,288 bit times, the MAC issues a Frame Abort status, and sets the excessive deferral error bit (EXDEFF) in the MAC MMC Transmit Interrupt (EMACMMCTXRIS) Register. If the Jumbo frame mode (JFEN) is enabled, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active carrier sense signal (CRS) on the MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0 and it is restarted. When this bit is clear, the deferral check function is disabled and the EMAC defers until the CRS signal goes inactive. This bit is only applicable in half-duplex mode.

0x0 = Deferral check function is disabled.

0x1 = Deferral check function is enabled.

Transmitter Enable. When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is clear, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames.

0x0 = MAC transmit state machine is disabled.

0x1 = MAC transmit state machine is enabled.

Receiver Enable. When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is clear, the MAC receive state machine is disabled after completion of the reception of the current frame, and does not receive any further frames from the MII.

0x0 = MAC receive state machine is disabled.

0x1 = MAC receive state machine is enabled.

Preamble Length for Transmit Frames. These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.

0x0 = 7 bytes of preamble

0x1 = 5 bytes of preamble

0x2 = 3 bytes of preamble

0x3 = Reserved