| 31 |
RIB |
R/W |
0x0 |
Rebuild Burst.
0x0 = During a retry, split or loss of bus, the DMA rebuilds the pending beats of any burst transfer with a continuous, uninterrupted burst until the last word, which is a single burst.
0x1 = During a retry, split or loss of bus, the DMA rebuilds the pending beats of any burst transfer initiated with a defined fixed burst of 1, 4, 8, or 16.
|
| 30-28 |
RESERVED |
R |
0x0 |
|
| 27 |
TXPR |
R/W |
0x0 |
Transmit Priority.
0x0 = The RX DMA has higher priority than the TX DMA during arbitration for the system bus.
0x1 = The TX DMA has higher priority than the RX DMA during arbitration for the system bus.
|
| 26 |
MB |
R/W |
0x0 |
Mixed Burst.
0x0 = Mixed burst is not enabled.
0x1 = If the FB bit is 0, the DMA starts all bursts of length more than 16 with a continuous undefined burst.For bursts less than 16, fixed and single bursts are used.
|
| 25 |
AAL |
R/W |
0x0 |
Address Aligned Beats.
0x0 = Address aligned transfers are not enabled.
0x1 = If the FB bit is set, the internal bus interface generates all bursts aligned to the start address least significant bits.If the FB bit is 0, the first burst is not aligned but subsequent bursts are aligned to the address.
|
| 24 |
8xPBL |
R/W |
0x0 |
8 x Programmable Burst Length (PBL) Mode.
0x0 = 8 x PBL mode is inactive.
0x1 = Bit field RPBL and bit field PBL are multiplied 8 times. Therefore, the DMA transfers the data in bursts of 8, 16, 32, 64, 128, and 256 words.
|
| 23 |
USP |
R/W |
0x0 |
Use Separate Programmable Burst Length (PBL).
0x0 = The PBL value in bits[13:8] is applicable for both the RX and TX DMA engines.
0x1 = RX DMA is uses the RPBL bit field as its defined programmable burst length and TX DMA uses the PBL bit field as its defined programmable burst length.
|
| 22-17 |
RPBL |
R/W |
0x1 |
RX DMA Programmable Burst Length (PBL). When the USP bit is 1, this field is used to indicate the maximum number of words to be transferred in one RX DMA transaction. This is the maximum value that is used in a single block read or write. The RX DMA always attempts to burst as specified in the RPBL bit each time it starts a burst transfer on the system bus. The application can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high.
|
| 16 |
FB |
R/W |
0x0 |
Fixed Burst. This bit defines if burst is used during burs transfer operations.
0x0 = The DMA bursts the entire length during burst transfers except for the last word, which is a single transfer.
0x1 = The DMA uses only single, or fixed bursts incremented by 4, 8, or 16 during normal bus transfers.
|
| 15-14 |
PR |
R/W |
0x0 |
Priority Ratio. These bits control the priority ratio in the weighted round-robin arbitration between the RX DMA and TX DMA. These bits are valid only when the DA bit in this register is clear. The priority ratio is RX:TX or TX:RX depending on whether the TXPR bit in this register is clear or set.
0x0 = The Priority Ratio is 1:1.
0x1 = The Priority Ratio is 2:1.
0x2 = The Priority Ratio is 3:1.
0x3 = The Priority Ratio is 4:1.
|
| 13-8 |
PBL |
R/W |
0x1 |
Programmable Burst Length.
These bits indicate the maximum number of beats to be transferred in one DMA transaction.
This is the maximum value that is used in a single block read or write. The DMA always attempts to burst as specified in PBL each time it starts a burst transfer on the bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for TX DMA transactions.
If the number of beats to be transferred is more than 32, then perform the following steps:
- Set the 8xPBL mode.
- Set the PBL value.
For example, if the maximum number of beats to be transferred is 64, then first set 8xPBL to 1 and then set PBL to 0x8.
|
| 7 |
ATDS |
R/W |
0x0 |
Alternate Descriptor Size.
0x0 = Descriptor size reverts back to four words
0x1 = Alternate descriptors, each eight words in length, are used.
|
| 6-2 |
DSL |
R/W |
0x0 |
Descriptor Skip Length. This bit specifies the number of words to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, then the descriptor table is taken as contiguous by the DMA in Ring mode.
|
| 1 |
DA |
R/W |
0x0 |
DMA Arbitration Scheme. This bit specifies the arbitration scheme between the transmit and receive paths of the DMA channel.
0x0 = Weighted round-robin with RX:TX or TX:RX.The priority between the paths is according to the priority specified in the PR bit field and priority weights specified in the TXPR bit.
0x1 = Fixed priority.The transmit path has priority over receive path when the TXPR bit is set. Otherwise, receive path has priority over the transmit path.
|
| 0 |
SWR |
R/W |
0x1 |
DMA Software Reset. The software reset function is driven by this bit. The reset operation is completed only when all resets in all active clock domains are deasserted. It is essential that all the PHY input clocks are present for the software reset completion. The time of the software reset operation depends on the frequency of the slowest active clock.
0x0 = Reset is completed. A value of 0 should be read before reprogramming any MAC registers after a reset
0x1 = MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation has completed in all of the MAC clock domains.
|