31 |
RA |
R/W |
0x0 |
Receive All. When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is clear, the Receiver module passes only those frames to the application that pass the SA or DA address filter.
0x0 = MAC RX module only passes frames that pass the SA or DA address filter.
0x1 = MAC RX module passes all received frames.
|
30-17 |
RESERVED |
R |
0x0 |
|
16 |
VTFE |
R/W |
0x0 |
VLAN Tag Filter Enable.
0x0 = MAC forwards all frames regardless of match status of VLAN Tag.
0x1 = MAC drops VLAN tagged frames that do not match VLAN tag comparison.
|
15-11 |
RESERVED |
R |
0x0 |
|
10 |
HPF |
R/W |
0x0 |
Hash or Perfect Filter. When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits in this register. When this bit is clear and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter.
0x0 = Address filter passes a frame if it matches perfect filtering or hash filtering.
0x1 = Address filter passes a frame only if it matches in the hash filter.
|
9 |
SAF |
R/W |
0x0 |
Source Address Filter Enable. When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison matches, then the SA match bit of Receive Status Word is set. When SA Match bit is set and the SA filter fails, the MAC drops the frame. When this bit is clear, the MAC forwards the received frame to the application with the updated SA Match bit of the Receive Status Word depending on the SA address comparison.
0x0 = Source address filter disabled.
0x1 = Source address filter enabled.
|
8 |
SAIF |
R/W |
0x0 |
Source Address (SA) Inverse Filtering. When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA address filter. When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter.
0x0 = Frames whose SA does not match the SA registers are marked as failing.
0x1 = Frames whose SA matches the SA registers are marked as failing.
|
7-6 |
PCF |
R/W |
0x0 |
Pass Control Frames. . These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). The following conditions should be true for the PAUSE control frames processing: Condition 1: The MAC is in full-duplex mode and flow control is enabled by setting the RFE bit of MAC Flow Control Register (EMACFLOWCTL). Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 (EMACADDR0x) Register when the UP bit of the (EMACFLOWCTL) is set. Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. This PCF field should be set to 0x1 only when Condition 1 is true; that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the PAUSE frame filtering may be inconsistent. When Condition 1 is false, the PAUSE frames are considered as generic control frames. Therefore, to pass all control frames (including PAUSE control frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 0x2 or 0x3 (as required by the application).
0x00 = The MAC filters all control frames from reaching application.
0x1 = MAC forwards all control frames except PAUSE control frames to application even if they fail the address filter.
0x2 = MAC forwards all control frames to application even if they fail the address Filter.
0x3 = MAC forwards control frames that pass the address Filter.
|
5 |
DBF |
R/W |
0x0 |
Disable Broadcast Frames. When this bit is set, the address filtering module (AFM) filters all incoming broadcast frames. In addition, it overrides all other filter settings.
0x0 = Address filtering module passes all received broadcast frames.
0x1 = Address filtering module filters all incoming broadcast frames.
|
4 |
PM |
R/W |
0x0 |
Pass All Multicast. When set, this bit indicates that all received frames with a multicast destination address (DA) (first bit in the destination address field is 1) are passed.
0x0 = Filtering of multicast frame depends on HMC bit in this register.
0x1 = All received frames with multicast DA are passed.
|
3 |
DAIF |
R/W |
0x0 |
Destination Address (DA) Inverse Filtering. When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames.
0x0 = Normal filtering of frames is performed.
0x1 = Inverse filtering mode is enabled for DA.
|
2 |
HMC |
R/W |
0x0 |
Hash Multicast.
0x0 = MAC performs a perfect destination address (DA) filtering for multicast frames.It compares the DA field with the values programmed in DA registers.
0x1 = MAC performs destination address filtering of received multicast frames according to the hash table.
|
1 |
HUC |
R/W |
0x0 |
Hash Unicast.
0x0 = MAC performs a perfect destination address filtering for unicast frames.It compares the DA field with the values programmed in DA registers.
0x1 = MAC performs destination address filtering of unicast frames according to the hash table.
|
0 |
PR |
R/W |
0x0 |
Promiscuous Mode. When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set.
0x0 = Incoming frames are filtered.
0x1 = All incoming frames are passed.
|