15.6.15 EMACIM Register (Offset = 0x3C) [reset = 0x0]
Ethernet MAC Interrupt Mask (EMACIM)
The Ethernet MAC Interrupt Mask (EMACIM) Register bits enables the application to mask the interrupt signal caused by the corresponding event in the Ethernet MAC Raw Interrupt Status (EMACRIS) Register.
EMACIM is shown in Figure 15-30 and described in Table 15-39.
Return to Summary Table.
Figure 15-30 EMACIM Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
LPI |
TSI |
RESERVED |
PMT |
RESERVED |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
R-0x0 |
|
Table 15-39 EMACIM Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-10 |
RESERVED |
R |
0x0 |
|
| 10 |
LPI |
R/W |
0x0 |
LPI Interrupt Mask.
0x0 = The LPI interrupt status bit in the MAC Raw Interrupt Status (EMACRIS) register is not masked and can cause an interrupt.
0x1 = The assertion of the LPI interrupt status bit in the MAC Raw Interrupt Status (EMACRIS) register is masked and does not cause an interrupt.
|
| 9 |
TSI |
R/W |
0x0 |
Timestamp Interrupt Mask.
0x0 = The TSI interrupt status bit in the MAC Raw Interrupt Status (EMACRIS) register is not masked and can cause an interrupt.
0x1 = The assertion of the TIS interrupt status bit in the MAC Raw Interrupt Status (EMACRIS) register is masked and does not cause an interrupt.
|
| 8-4 |
RESERVED |
R |
0x0 |
|
| 3 |
PMT |
R/W |
0x0 |
PMT Interrupt Mask.
0x0 = The PMT interrupt status bit in the MAC Raw Interrupt Status (EMACRIS) register is not masked and can cause an interrupt.
0x1 = The assertion of the PMT interrupt status bit in the MAC Raw Interrupt Status (EMACRIS) register is masked and does not cause an interrupt.
|
| 2-0 |
RESERVED |
R |
0x0 |
|