SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
LPI Control and Status (EMACLPICTLSTAT)
The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read.
EMACRIS is shown in Figure 15-29 and described in Table 15-38.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | LPITXA | PLSEN | PLS | LPIEN | |||
| R-0x0 | RW-0x0 | R/W-0x0 | RW-0x0 | RW-0x0 | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RLPIST | TLPIST | |||||
| R-0x0 | R-0x0 | R-0x0 | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RLPIEX | RLPIEN | TLPIEX | TLPIEN | |||
| R-0x0 | R-0x0 | R-0x0 | R-0x0 | R-0x0 | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R | 0x0 | |
| 19 | LPITXA | RW | 0x0 | LPI TX Automate.
This bit controls the behavior of the MAC when it is entering or leaving the LPI mode on transmit. This bit is not functional in the GMAC-CORE configuration in which the TX clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI mode. If the FTF bit is 1 in the EMACDMAOPMODE register when the MAC is in the LPI mode, the MAC exits the LPI mode. When the FTF bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. 0x0 = Disabled 0x1 = Enabled |
| 18 | PLSEN | RW | 0x0 | PHY Link Status Enable.
This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS timer. When set, the MAC uses the link status bits and the PLS bit for the LPI LS timer trigger. When cleared, the MAC ignores the link-status bits and uses only the PLS bit. This bit is reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. 0x0 = MAC ignores link status bits 0x1 = MAC uses link status bits |
| 17 | PLS | RW | 0x0 | PHY Link Status.
This bit indicates the link status of the PHY. The MAC transmitter asserts the LPI pattern only when the link status is up (OK) at least for the time indicated by the LPI LS timer. 0x0 = Link down 0x1 = Link up (OK) |
| 16 | LPIEN | RW | 0x0 | LPI Enable.
When set, this bit instructs the MAC transmitter to enter the LPI mode. When reset, this bit instructs the MAC to exit the LPI mode and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI mode because of the arrival of a new packet for transmission. 0x0 = MAC transmitter exits LPI mode 0x1 = MAC transmitter enters LPI mode |
| 15-10 | RESERVED | R | 0x0 | |
| 9 | RLPIST | R | 0x0 | Receive LPI Mode.
0x0 = MAC is not receiving LPI pattern 0x1 = MAC is receiving LPI pattern |
| 8 | TLPIST | R | 0x0 | Transmit LPI Mode.
0x0 = MAC is not transmitting LPI pattern 0x1 = MAC is transmitting LPI pattern |
| 7-4 | RESERVED | R | 0x0 | |
| 3 | RLPIEX | R | 0x0 | Receive LPI Exit.
This bit is cleared by a read into this register. 0x0 = MAC receiver is receiving LPI patterns 0x1 = MAC receiver has stopped receiving the LPI pattern, exited LPI mode, and resumed normal reception. Note: This bit may not be set if the MAC stops receiving the LPI pattern for a very short duration, such as less than 3 clock cycles of l3_sp_clk. |
| 2 | RLPIEN | R | 0x0 | Receive LPI Entry.
This bit is cleared by a read into this register. 0x0 = MAC receiver not in LPI mode 0x1 = MAC receiver received an LPI pattern and entered LPI mode Note: This bit may not beset if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of l3_sp_clk. |
| 1 | TLPIEX | R | 0x0 | Transmit LPI Exit.
This bit is cleared by a read into this register. 0x0 = MAC transmitter not in LPI mode 0x1 = MAC transmitter exited the LPI mode after the user software has cleared the LPIEN bit and the LPI TW timer has expired |
| 0 | TLPIEN | R | 0x0 | Transmit LPI Entry.
This bit is cleared by a read into this register. 0x0 = MAC transmitter not in LPI mode 0x1 = MAC transmitter entered the LPI mode because of the setting of the LPIEN bit |