15.6.62 EMACMFBOC Register (Offset = 0xC20) [reset = 0x0]
Ethernet MAC Missed Frame and Buffer Overflow Counter (EMACMFBOC)
The DMA maintains two counters to track the number of frames missed during reception. This register reports the current value of the counters. The counter is used for diagnostic purposes. The MISFRMCNT field indicates missed frames because of the host buffer being unavailable. The OVFFRMCNT field indicates missed frames because of buffer overflow conditions (MTL and MAC) and runt frames (good frames of less than 64 bytes) dropped by the MTL.
EMACMFBOC is shown in Figure 15-77 and described in Table 15-87.
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Figure 15-77 EMACMFBOC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
OVFCNTOVF |
OVFFRMCNT |
| R-0x0 |
R-0x0 |
R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| OVFFRMCNT |
MISCNTOVF |
| R-0x0 |
R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| MISFRMCNT |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| MISFRMCNT |
| R-0x0 |
|
Table 15-87 EMACMFBOC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-29 |
RESERVED |
R |
0x0 |
|
| 28 |
OVFCNTOVF |
R |
0x0 |
Overflow Bit for FIFO Overflow Counter. This bit is set every time the overflow frame counter (bits [27:17]) overflows; that is, the RX FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all zeros and this bit indicates the rollover happened.
|
| 27-17 |
OVFFRMCNT |
R |
0x0 |
Overflow Frame Counter. This field indicates the number of frames missed by the application. This counter is incremented each time the TX/RX Controller indicates overflow. This counter is cleared when the TX/RX Controller accepts data.
|
| 16 |
MISCNTOVF |
R |
0x0 |
Overflow bit for Missed Frame Counter. This bit is set every time the Missed Frame Counter (bits [15:0]) overflows; which means the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed Frame Counter is reset to all zeros and this bit indicates that the rollover happened.
|
| 15-0 |
MISFRMCNT |
R |
0x0 |
Missed Frame Counter. This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. This counter is cleared when the DMA accepts frames.
|