15.6.28 EMACMMCRXIM Register (Offset = 0x10C) [reset = 0x0]
Ethernet MAC MMC Receive Interrupt Mask (EMACMMCRXIM)
The MAC MMC Receive Interrupt Mask (EMACMMCRXIM) register maintains the masks for the interrupts generated when the receive statistic counters reach half of their maximum value, or maximum value. This register is 32-bits wide.
EMACMMCRXIM is shown in Figure 15-43 and described in Table 15-52.
Return to Summary Table.
Figure 15-43 EMACMMCRXIM Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
UCGF |
RESERVED |
| R-0x0 |
R/W-0x0 |
R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
ALGNERR |
CRCERR |
RESERVED |
GBF |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
Table 15-52 EMACMMCRXIM Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-18 |
RESERVED |
R |
0x0 |
|
| 17 |
UCGF |
R/W |
0x0 |
MMC Receive Unicast Good Frame Counter Interrupt Mask.
0x0 = An interrupt is sent to the interrupt controller when the UCGF bit in the EMACMMCRXRIS register is set.
0x1 = The UCGF interrupt is suppressed and not sent to the interrupt controller.
|
| 16-7 |
RESERVED |
R |
0x0 |
|
| 6 |
ALGNERR |
R/W |
0x0 |
MMC Receive Alignment Error Frame Counter Interrupt Mask.
0x0 = An interrupt is sent to the interrupt controller when the ALGNERR bit in the EMACMMCRXRIS register is set.
0x1 = The ALGNERR interrupt is suppressed and not sent to the interrupt controller.
|
| 5 |
CRCERR |
R/W |
0x0 |
MMC Receive CRC Error Frame Counter Interrupt Mask.
0x0 = An interrupt is sent to the interrupt controller when the CRCERR bit in the EMACMMCRXRIS register is set.
0x1 = The CRCERR interrupt is suppressed and not sent to the interrupt controller.
|
| 4-1 |
RESERVED |
R |
0x0 |
|
| 0 |
GBF |
R/W |
0x0 |
MMC Receive Good Bad Frame Counter Interrupt Mask.
0x0 = An interrupt is sent to the interrupt controller when the GBF bit in the EMACMMCRXRIS register is set.
0x1 = The GBF interrupt is suppressed and not sent to the interrupt controller.
|