15.6.29 EMACMMCTXIM Register (Offset = 0x110) [reset = 0x0]
Ethernet MAC MMC Transmit Interrupt Mask (EMACMMCTXIM)
The MAC MMC Transmit Interrupt Mask (EMACMMCTXIM) register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or maximum value. This register is 32-bits wide.
EMACMMCTXIM is shown in Figure 15-44 and described in Table 15-53.
Return to Summary Table.
Figure 15-44 EMACMMCTXIM Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
OCTCNT |
RESERVED |
| R-0x0 |
R/W-0x0 |
R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| MCOLLGF |
SCOLLGF |
RESERVED |
| R/W-0x0 |
R/W-0x0 |
R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
GBF |
RESERVED |
| R-0x0 |
R/W-0x0 |
R-0x0 |
|
Table 15-53 EMACMMCTXIM Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-21 |
RESERVED |
R |
0x0 |
|
| 20 |
OCTCNT |
R/W |
0x0 |
MMC Transmit Good Octet Counter Interrupt Mask.
0x0 = An interrupt is sent to the interrupt controller when the OCTCNT bit in the EMACMMCTXRIS register is set.
0x1 = The OCTCNT interrupt is suppressed and not sent to the interrupt controller.
|
| 19-16 |
RESERVED |
R |
0x0 |
|
| 15 |
MCOLLGF |
R/W |
0x0 |
MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask.
0x0 = An interrupt is sent to the interrupt controller when the MCOLLGF bit in the EMACMMCTXRIS register is set.
0x1 = The MCOLLGF interrupt is suppressed and not sent to the interrupt controller.
|
| 14 |
SCOLLGF |
R/W |
0x0 |
MMC Transmit Single Collision Good Frame Counter Interrupt Mask.
0x0 = An interrupt is sent to the interrupt controller when the SCOLLGF bit in the EMACMMCTXRIS register is set.
0x1 = The SCOLLGF interrupt is suppressed and not sent to the interrupt controller.
|
| 13-2 |
RESERVED |
R |
0x0 |
|
| 1 |
GBF |
R/W |
0x0 |
MMC Transmit Good Bad Frame Counter Interrupt Mask.
0x0 = An interrupt is sent to the interrupt controller when the GBF bit in the EMACMMCTXRIS register is set.
0x1 = The GBF interrupt is suppressed and not sent to the interrupt controller.
|
| 0 |
RESERVED |
R |
0x0 |
|