15.6.27 EMACMMCTXRIS Register (Offset = 0x108) [reset = 0x0]
Ethernet MAC MMC Transmit Raw Interrupt Status (EMACMMCTXRIS)
The MAC MMC Transmit Interrupt (EMACMMCTXRIS) register maintains the interrupts generated when transmit statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter), and the maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When the CNTSTPRO bit is set in the MAC MMC Control (EMACMMCCTRL) register, interrupts are set but the counter remains at all-ones. The EMACMMCTXRIS register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.
EMACMMCTXRIS is shown in Figure 15-42 and described in Table 15-51.
Return to Summary Table.
Figure 15-42 EMACMMCTXRIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
OCTCNT |
RESERVED |
| R-0x0 |
R-0x0 |
R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| MCOLLGF |
SCOLLGF |
RESERVED |
| R-0x0 |
R-0x0 |
R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
GBF |
RESERVED |
| R-0x0 |
R-0x0 |
R-0x0 |
|
Table 15-51 EMACMMCTXRIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-21 |
RESERVED |
R |
0x0 |
|
| 20 |
OCTCNT |
R |
0x0 |
Octet Counter Interrupt Status.
0x0 = The Ethernet MAC Transmit Octet Count Good (EMACTXOCTCNTG) register has not reached half of the maximum value or the maximum value.
0x1 = The Ethernet MAC Transmit Octet Count Good (EMACTXOCTCNTG) register has reached half of the maximum value or the maximum value.
|
| 19-16 |
RESERVED |
R |
0x0 |
|
| 15 |
MCOLLGF |
R |
0x0 |
MMC Transmit Multiple Collision Good Frame Counter Interrupt Status.
0x0 = The Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions (EMACTXCNTMCOL) register has not reached half of the maximum value or the maximum value.
0x1 = The Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions (EMACTXCNTMCOL) register has reached half of the maximum value or the maximum value.
|
| 14 |
SCOLLGF |
R |
0x0 |
MMC Transmit Single Collision Good Frame Counter Interrupt Status.
0x0 = The Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision (EMACTXCNTSCOL) register has not reached half of the maximum value or the maximum value.
0x1 = The Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision (EMACTXCNTSCOL) register has reached half of the maximum value or the maximum value.
|
| 13-2 |
RESERVED |
R |
0x0 |
|
| 1 |
GBF |
R |
0x0 |
MMC Transmit Good Bad Frame Counter Interrupt Status.
0x0 = The Ethernet MAC Transmit Frame Count for Good and Bad Frames (EMACTXCNTGB) register has not reached half of the maximum value or the maximum value.
0x1 = The Ethernet MAC Transmit Frame Count for Good and Bad Frames (EMACTXCNTGB) register has reached half of the maximum value or the maximum value.
|
| 0 |
RESERVED |
R |
0x0 |
|