| 31 |
PHYEXT |
R/W |
0x0 |
PHY Select. This bit is used to select whether the internal or an external PHY is used.
0x0 = Internal PHY
0x1 = External PHY
|
| 30-28 |
PINTFS |
R/W |
0x0 |
Ethernet Interface Select. This field selects the PHY interface used by the MAC. This input is sampled during reset and an update to this register field must result in the MAC undergoing a reset event. This field has the following encoded values:
0x0 = MII (default) Used for internal PHY or external PHY connected via MII.
0x1 = Reserved
0x2 = Reserved
0x3 = Reserved
0x4 = RMII: Used for external PHY connected via RMII.
0x5 = Reserved
0x6 = Reserved
0x7 = Reserved
|
| 27-26 |
RESERVED |
R |
0x0 |
|
| 25 |
DIGRESTART |
R/W |
0x0 |
PHY Soft Restart. This bit allows the user to restart the PHY. Asserting this bit causes the PHY logic and internal register to reset to initial conditions. This bit does not affect the configuration bits provided by the EMACPC register, which are stored in the PHY following a chip reset. To initiate the soft reset to the PHY, this bit must be written to a 1 and written again to a 0.
|
| 24 |
NIBDETDIS |
R |
0x0 |
Odd Nibble TXER Detection Disable. This bit is sampled on the deassertion of the PHY reset signal and is used as the default for the ODDNDETDIS bit of the Ethernet PHY Configuration 2 (EPHYCFG2) register, PHY offset 0x00A.
|
| 23 |
RXERIDLE |
R/W |
0x1 |
RXER Detection During Idle. This bit is sampled on the deassertion of the PHY reset signal and is used as the default for the RXERRIDLE bit of the Ethernet PHY Configuration 2 (EPHYCFG2) register, PHY offset 0x00A.
|
| 22 |
ISOMIILL |
R/W |
0x0 |
Isolate MII in Link Loss. This bit is sampled on the deassertion of the PHY reset signal and is used as the default for the ISOMIILL bit of the Ethernet PHY Configuration 2 (EPHYCFG2) register, PHY offset 0x00A.
|
| 21 |
LRR |
R/W |
0x0 |
Link Loss Recovery. This bit is sampled on the deassertion of the PHY reset signal and is used as the default for the LLR bit of the Ethernet PHY Configuration 1 (EPHYCFG1) register, PHY offset 0x009.
|
| 20 |
TDRRUN |
R/W |
0x0 |
TDR Auto Run. This bit is sampled on the deassertion of the PHY reset signal and is used as the default for the TDRAR bit of the Ethernet PHY Configuration 1 (EPHYCFG1) register, PHY offset 0x009.
|
| 19-15 |
FASTLDMODE |
R/W |
0x0 |
Fast Link Down Mode. These bits are sampled on the deassertion of the PHY reset signal and are used as the default for the FLDWNM bit field of the Ethernet PHY Configuration 3 (EPHYCFG3) register, PHY offset 0x00B.
|
| 14 |
POLSWAP |
R/W |
0x0 |
Polarity Swap. This bit is sampled on the deassertion of the PHY reset signal and is used as the default for the POLSWAP bit of the Ethernet PHY Configuration 3 (EPHYCFG3) register, PHY offset 0x00B.
|
| 13 |
MDISWAP |
R/W |
0x0 |
MDI Swap. This bit is sampled on the deassertion of the PHY reset signal and is used as the default for the MDIMDIXS bit of the Ethernet PHY Configuration 3 (EPHYCFG3) register, PHY offset 0x00B.
|
| 12 |
RBSTMDIX |
R/W |
0x0 |
Robust Auto MDI-X. This bit is sampled on the deassertion of the PHY reset signal and is used as the default for the RAMDIX bit of the Ethernet PHY Configuration 1 (EPHYCFG1) register, PHY offset 0x009.
|
| 11 |
FASTMDIX |
R |
0x0 |
Fast Auto MDI-X. This bit is sampled on the deassertion of the PHY reset signal and is used as the default for the FAMDIX bit of the Ethernet PHY Configuration 1 (EPHYCFG1) register, PHY offset 0x009.
|
| 10 |
MDIXEN |
R/W |
0x1 |
MDIX Enable. This bit is sampled on the deassertion of the PHY reset signal and is used to determine whether automatic MDI/MDIX crossover is enabled.
0x0 = Disable automatic crossover.
0x1 = Enable automatic crossover.
|
| 9 |
FASTRXDV |
R/W |
0x0 |
Fast RXDV Detection. This bit is sampled on the deassertion of the PHY reset signal and is used to select whether fast RXDV detection is enabled in the PHY.
0x0 = Disable fast RXDV detection.
0x1 = Enable fast RXDV detection.
|
| 8 |
FASTLUPD |
R/W |
0x0 |
FAST Link-Up in Parallel Detect. This bit is sampled on the deassertion of the PHY reset signal and is used as the default value for the FLUPPD bit of the Ethernet PHY Configuration 2 (EPHYCFG2) register, PHY offset 0x00A.
|
| 7 |
EXTFD |
R/W |
0x0 |
Extended Full Duplex Ability. This bit is sampled on the deassertion of the PHY reset signal and is used as the default value for the EXTFD bit of the Ethernet PHY Configuration 2 (EPHYCFG2) register, PHY offset 0x00A.
|
| 6 |
FASTANEN |
R/W |
0x0 |
Fast Auto Negotiation Enable. This bit is sampled on the deassertion of the PHY reset signal and is used as the default for the FASTANEN bit of the Ethernet PHY Configuration 1 (EPHYCFG1) register, PHY offset 0x009.
|
| 5-4 |
FASTANSEL |
R/W |
0x0 |
Fast Auto Negotiation Select. These bits are sampled on the deassertion of the PHY reset signal and are used as the defaults for the FANSEL bit field of the Ethernet PHY Configuration 1 (EPHYCFG1) register, PHY offset 0x009.
|
| 3 |
ANEN |
R/W |
0x1 |
Auto-Negotiation Enable. This bit is sampled on the deassertion of the PHY reset signal and is to select whether auto-negotiation is enabled.
0x0 = Auto-negotiation disabled.
0x1 = Auto-negotiation enabled.
|
| 2-1 |
ANMODE |
R/W |
0x3 |
Auto Negotiation Mode. These bits are sampled on the deassertion of the PHY reset signal and are used to determine the auto-negotiation mode of the PHY.
0x0 = When ANEN = 0x0, the mode is 10Base-T, Half-Duplex. When ANEN =0x1, the mode is 10Base-T, Half/Full-Duplex.
0x1 = When ANEN = 0x0, the mode is 10Base-T, Full-Duplex. When ANEN =0x1, the mode is 100Base-TX, Half/Full-Duplex.
0x2 = When ANEN = 0x0, the mode is 100Base-TX, Half-DuplexWhen ANEN =0x1, the mode is 10Base-T,Half-Duplex 100Base-TX, Half-Duplex
0x3 = When ANEN = 0x0, the mode is 100Base-TX, Full-Duplex. When ANEN = 0x1, the mode is 10Base-T, Half/Full-Duplex 100Base-TX, Half/Full-Duplex.
|
| 0 |
PHYHOLD |
R/W |
0x0 |
Ethernet PHY Hold. This bit is sampled on the deassertion of the PHY reset signal and is used to keep the PHY from transmitting energy on the line.
0x0 = PHY transmits energy on the line.
0x1 = PHY is held off from transmitting energy on the line.
|