SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Ethernet MAC Power Domain Status (EMACPDS)
This register provides the status of power to the EMAC SRAM array.
NOTE
The EMAC memory array does not support retention and can only be turned on and off. Memory array off is supported only when the power domain is off. If the memory array is currently turned on (PWRCTL = 0x3) and the power control to the EMAC is subsequently removed by clearing the P0 bit of the PCEMAC register, the event causes the memory array to turn off and the MEMSTAT bit in the EMACPDS register to be 0x0 (array off).
EMACPDS is shown in Figure 4-40 and described in Table 4-47.
Return to Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | MEMSTAT | PWRSTAT | ||||
R-0x0 | R-0x3 | R-0x3 | R-0x3 | ||||