SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Ethernet MAC Receive Descriptor List Address (EMACRXDLADDR)
The Ethernet MAC Receive Descriptor List Address (EMACRXDLADDR) register points to the start of the Receive Descriptor List. The descriptor lists reside in the host's physical memory space and must be word-aligned. The DMA internally converts it to a 32-bit aligned address by making the two lease significant bits zero. Writing to this register is permitted only when the DMA receive transaction has stopped (SR = 0 n the MAC DMA Operation Mode (EMACDMAOPMODE) register). When stopped, this register must be written with a new descriptor list address before the receive Start command is given. When you set the SR bit to 1, the DMA takes the newly programmed descriptor base address. If this register is not changed when the SR bit is set to 0, then the DMA uses the already existing descriptor address.
EMACRXDLADDR is shown in Figure 15-72 and described in Table 15-82.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
STRXLIST | |||||||
R/W-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
STRXLIST | |||||||
R/W-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
STRXLIST | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STRXLIST | RESERVED | ||||||
R/W-0x0 | R-0x0 | ||||||