31-26 |
RESERVED |
R |
0x0 |
|
25 |
TXFF |
R |
0x0 |
TX/RX Controller TX FIFO Full Status.
0x0 = The TX/RX Controller TX FIFO is not full.
0x1 = The TX/RX Controller TX FIFO is full. Therefore, the TX/RX Controller cannot accept any more frames for transmission.
|
24 |
TXFE |
R |
0x0 |
TX/RX Controller TX FIFO Not Empty Status.
0x0 = TX/RX Controller TX FIFO is empty.
0x1 = TX/RX Controller TX FIFO is not empty and some data is left for transmission.
|
23 |
RESERVED |
R |
0x0 |
|
22 |
TWC |
R |
0x0 |
TX/RX Controller TX FIFO Write Controller Active Status.
0x0 = TX/RX Controller's TX FIFO write controller is inactive.
0x1 = TX/RX Controller's TX FIFO write controller is active and transferring data to the TX FIFO.
|
21-20 |
TRC |
R |
0x0 |
TX/RX Controller's TX FIFO Read Controller Status. This field indicates the state of the TX FIFO read controller:
0x0 = IDLE state
0x1 = READ state (transferring data to MAC transmitter)
0x2 = Waiting for TX Status from MAC transmitter
0x3 = Writing the received TX Status or flushing the TX FIFO
|
19 |
TXPAUSED |
R |
0x0 |
MAC Transmitter PAUSE.
0x0 = MAC transmitter is not in PAUSE mode.
0x1 = Indicates that the MAC transmitter is in the PAUSE condition (in the full-duplex only mode) and hence does not schedule any frame for transmission.
|
18-17 |
TFC |
R |
0x0 |
MAC Transmit Frame Controller Status. This field indicates the state of the MAC Transmit Frame Controller module:
0x0 = IDLE state
0x1 = Waiting for status of previous frame or IFG or backoff period to be over
0x2 = Generating and transmitting a PAUSE control frame (in the full-duplex mode)
0x3 = Transferring input frame for transmission
|
16 |
TPE |
R |
0x0 |
MAC MII Transmit Protocol Engine Status.
0x0 = MAC MII transmit protocol engine is not actively transmitting data.
0x1 = MAC MII transmit protocol engine is actively transmitting data and is not in the IDLE state.
|
15-10 |
RESERVED |
R |
0x0 |
|
9-8 |
RXF |
R |
0x0 |
TX/RX Controller RX FIFO Fill-level Status. This field gives the status of the fill-level of the RX FIFO. The FIFO threshold is programmed by the TCC field in the Ethernet MAC DMA Operation Mode (EMACDMAOPMODE) register.
0x0 = RX FIFO Empty
0x1 = RX FIFO fill level is below the flow-control deactivate threshold
0x2 = RX FIFO fill level is above the flow-control activate threshold
0x3 = RX FIFO Full
|
7 |
RESERVED |
R |
0x0 |
|
6-5 |
RRC |
R |
0x0 |
TX/RX Controller Read Controller State. This field gives the state of the RX FIFO read Controller.
0x0 = IDLE state
0x1 = Reading frame data
0x2 = Reading frame status (or timestamp)
0x3 = Flushing the frame data and status
|
4 |
RWC |
R |
0x0 |
TX/RX Controller RX FIFO Write Controller Active Status.
0x0 = The MTL RX FIFO Write Controller is inactive.
0x1 = MTL RX FIFO Write Controller is active and is transferring a received frame to the FIFO.
|
3 |
RESERVED |
R |
0x0 |
|
2-1 |
RFCFC |
R |
0x0 |
MAC Receive Frame Controller FIFO Status. When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module.
|
0 |
RPE |
R |
0x0 |
MAC MII Receive Protocol Engine Status.
0x0 = MAC MII receive protocol engine is not actively receiving data.
0x1 = Indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state.
|