15.6.48 EMACTARGNANO Register (Offset = 0x720) [reset = 0x0]
Ethernet MAC Target Time Nanoseconds (EMACTARGNANO)
The MAC Target Time Seconds (EMACTARGSEC) register, along with the MAC Target Time Nanoseconds (EMACTARGNANO) register, is used to schedule an interrupt event.
EMACTARGNANO is shown in Figure 15-63 and described in Table 15-72.
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Figure 15-63 EMACTARGNANO Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| TRGTBUSY |
TTSLO |
| R/W-0x0 |
R/W-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| TTSLO |
| R/W-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| TTSLO |
| R/W-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| TTSLO |
| R/W-0x0 |
|
Table 15-72 EMACTARGNANO Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31 |
TRGTBUSY |
R/W |
0x0 |
Target Time Register Busy. This bit is set and cleared by the MAC.
0x0 = The Ethernet MAC Target Time Seconds/Nanoseconds (EMACTARGSEC/EMACTARGNANO) registers are not busy.
0x1 = The Ethernet MAC Target Time Seconds/Nanoseconds (EMACTARGSEC/EMACTARGNANO) registers are busy. This bit is set when the PPSCTRL field in the EMACPPSCTRL register is programmed to 0x2 or 0x3 and the MAC is instructed to synchronize the EMACTARGSEC/EMACTARGNANO registers to the PTP clock domain. The EMACTARGSEC and EMACTARGNANO registers must not be updated when this bit is read as 1.
|
| 30-0 |
TTSLO |
R/W |
0x0 |
Target Timestamp Low Register. This register stores the time in (signed) nanoseconds. When the value of the timestamp matches both EMACTARGx registers, the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on the TRGMODS0 field in the MAC PPS Control (EMACPPSCTRL) register. This value should not exceed 0x3B9A.C9FF when DGTLBIN is set in the EMACTIMSTCTRL register. The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value.
|