SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Interrupt 0-31 Set Enable (EN0), offset 0x100
Interrupt 32-63 Set Enable (EN1), offset 0x104
Interrupt 64-95 Set Enable (EN2), offset 0x108
\Interrupt 96-113 Set Enable (EN3), offset 0x10C
NOTE
This register can only be accessed from privileged mode.
The ENn registers enable interrupts and show which interrupts are enabled. Bit 0 of EN0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of EN1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of EN2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of EN3 corresponds to Interrupt 96; bit 17 corresponds to Interrupt 113.
See for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.
EN0 is shown in Figure 2-6 and described in Table 2-16.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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