When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it indicates that the descriptor is owned by the Host. The DMA clears this bit either when it completes the frame transmission or when the buffers allocated in the descriptor are empty. The ownership bit of the First Descriptor of the frame should be set after all subsequent descriptors belonging to the same frame have been set. This avoids a possible race condition between fetching a descriptor and the driver setting an ownership bit.

When set this bit sets the Transmit Interrupt (TI) bit in the EMACDMARIS register when the frame contained in this descriptor has been transmitted.

When set, this bit indicates that the buffer contains the last segment of the frame. When this bit is set, the TBS1 or TBS2 field in TDES1 should have a non-zero value.

When set, this bit indicates that the buffer contains the first segment of a frame.

When set, the MAC does not append a Cyclic Redundancy Check (CRC) to the end of the transmitted frame. This is valid only when the first segment (TDES0[28]) is set.

When set, the MAC does not automatically add padding to a frame shorter than 64 bytes. When this bit is reset, the DMA automatically adds padding and CRC to a frame shorter than 64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]) bit. This is valid only when the first segment (TDES0[28]) is set.

When set, this bit enables IEEE1588 hardware timestamping for the transmit frame referenced by the descriptor. This bit is only valid when the First Segment Control bit (TDES0[28] is set.

When set, the MAC replaces the last four bytes of the transmitted packet with recalculated CRC bytes. The CPU should ensure that the CRC bytes are present in the frame being transferred from the Transmit Buffer. CRC replacement is done only when Bit 27 (DC) is set to 1.

These bits control the insertion of checksums in Ethernet frames that encapsulate TCP, UDP, or ICMP over IPv4 or IPv6. This field is valid when the First Segment control bit (TDES0[28]) is set.

• 0x0 = Do nothing. Checksum Engine bypassed.
• 0x1 = Insert IPv4 header checksum. Use this value to insert IPv4 header checksum when the frame encapsulates an IPv4 datagram.
• 0x2 = Insert TCP/UDP/ICMP checksum. The checksum is calculated over the TCP, UDP, or ICMP segment only and the TCP, UDP, or ICMP pseudo-header checksum is assumed to be present in the corresponding input frame's Checksum field. An IPv4 header checksum is also inserted if the encapsulated datagram conforms to IPv4.
• 0x3 = Insert a TCP/UDP/ICMP checksum that is fully calculated in this engine. The TCP, UDP, or ICMP pseudo-header is included in the checksum calculation, and the input frame's corresponding Checksum field has an all-zero value. An IPv4 Header checksum is also inserted if the encapsulated datagram conforms to IPv4.

The Checksum engine detects whether the TCP, UDP, or ICMP segment is encapsulated in IPv4 or IPv6 and processes its data accordingly.

When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the base address of the list, creating a descriptor ring.

When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a "don't care" value. TDES0[21] takes precedence over TDES0[20].

When set, these bits request the MAC to perform VLAN tagging or untagging before transmitting the frames. If the frame is modified for VLAN tags, the MAC automatically recalculates and replaces the CRC bytes.

The values of this field are as follows:

• 0x0 = Do not add a VLAN tag
• 0x1 = Remove the VLAN tag from the frames before transmission.
• 0x2 = Insert a VLAN tag with the tag value programmed in the Ethernet MAC VLAN Tag Inclusion or Replacement (EMACVLNINCREP) register, offset 0x584.
• 0x3 = Replace the VLAN tag in frame with the tag value programmed in the EMACVLNINCREP register. This field is valid when the First Segment control bit (TDES0[28]) is set.

This status bit indicates that a timestamp has been captured for the corresponding transmit frame. When this bit is set, TDES6 and TDES7 have timestamp values that were captured for the transmit frame. This field is valid only when the Last Segment control bit (TDES0[29]) in a descriptor is set.

When set, this bit indicates that the Checksum Offload engine detected an IP header error. This bit is valid only when TX Checksum Offload is enabled. Otherwise, it is reserved. If the Checksum Offload Engine detects an IP header error, it still inserts an IPv4 header checksum if the Ethernet Type field indicates an IPv4 payload.

Indicates the logical OR of the following bits:

• TDES0[16]: IP Header Error
• TDES0[14]: Jabber Timeout
• TDES0[13]: Frame Flush
• TDES0[12]: Payload Checksum Error
• TDES0[11]: Loss of Carrier
• TDES0[10]: No Carrier
• TDES0[9]: Late Collision
• TDES0[8]: Excessive Collision
• TDES0[2]: Excessive Deferral
• TDES0[1]: Underflow error

When set, this bit indicates that the MAC transmitter has experienced a jabber time-out. This bit can only be set when the Jabber Disabled (JD) bit of the EMACCFG register is clear.

When set, this bit indicates that the DMA flushed the frame because of a software flush command given by the CPU.

When set, this bit indicates that MAC transmitter detected an error in the TCP, UDP, or ICMP IP datagram payload. The transmitter checks the payload length received in the IPv4 or IPv6 header against the actual number of TCP, UDP, or ICMP packet bytes received from the application and issues an error status in case of a mismatch.

When set, this bit indicates that Loss of Carrier occurred during frame transmission. This is valid only for the frames transmitted without collision and when the MAC operates in half-duplex mode.

When set, this bit indicates that the carrier sense signal form the PHY was not asserted during transmission.

When set, this bit indicates that frame transmission was aborted due to a collision occurring after the collision window (64 byte times including Preamble in MII Mode). Not valid if Underflow Error (bit 1) is set.

When set, this bit indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. If the Disable Retry (DR) bit in EMACCFG register is set, this bit is set after the first collision and the transmission of the frame is aborted.

When set, this bit indicates that the transmitted frame was a VLAN-type frame.

This 4-bit counter value indicates the number of collisions occurring before the frame was transmitted. The count is not valid when the Excessive Collision bit (TDES0[8]) is set.

When set, this bit indicates that the transmission has ended because of excessive deferral of over 24288 bit times (155680 bits times when Jumbo Frame is enabled). This bit is dependent on the Deferral Check (DC) bit being enabled in the EMACCFG register.

When set, this bit indicates that the MAC aborted the frame because the data arrived late from system memory. Underflow Error indicates that the DMA encountered an empty Transmit Buffer while transmitting the frame. The transmission process enters the suspended state and sets both Transmit Underflow (UNF) and Transmit Interrupt (TI) bit in the EMACDMARIS register.

This bit indicates the deferral mechanism is active and that the transmit state machine sends a JAM pattern to defer reception when it senses a carrier before a normal transmission is scheduled. This bit is only valid in half-duplex mode.

SAIC: SA Insertion Control

These bits request the MAC to add or replace the Source Address field in the Ethernet frame with the value given in the MAC Address 0 register. If the Source Address field is modified in a frame, the MAC automatically recalculates and replaces the CRC bytes.

The Bit 31 specifies the MAC Address Register (1 or 0) value that is used for Source Address insertion or replacement. The following list describes the values of bits [30:29]:

• 0x0 = Do not include the source address.
• 0x1 = Insert the source address. For reliable transmission, the application must provide frames without source addresses.
• 0x2 = Replace the source address. For reliable transmission, the application must provide frames with source addresses.
• 0x3 = Reserved

These bits are valid when the First Segment control bit (TDES0[28]) is set.

TBS2: Transmit Buffer 2 Size

This field indicates the second data buffer size in bytes. This field is not valid if TDES0[20] is set.

TBS1: Transmit Buffer 1 Size

These bits indicate the first data buffer byte size, in bytes. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or the next descriptor, depending on the value of TCH (TDES0[20]).

Buffer 1 Address Pointer

These bits indicate the physical address of Buffer 1. There is no limitation on the buffer address alignment. Note that the buffers are stored in SRAM.

Buffer 2 Address Pointer (Next Descriptor Address)

Indicates the physical address of Buffer 2 when a descriptor ring structure is used. If the Second Address Chained (TDES0[20]) bit is set, this address contains the pointer to the physical memory where the Next Descriptor is present. The buffer address pointer must be aligned to the bus width only when TDES0[20] is set.

Note that the buffers are stored in SRAM.

TTSL: Transmit Frame Timestamp Low

This field is updated by DMA with the least significant 32 bits of the timestamp captured for the corresponding transmit frame. This field has the timestamp only if the Last Segment bit (LS), TDES0[29], in the descriptor is set and Timestamp status (TTSS) bit, TDES0[17], is set.

TTSH: Transmit Frame Timestamp High

This field is updated by DMA with the most significant 32 bits of the timestamp captured for the corresponding receive frame. This field has the timestamp only if the Last Segment bit (LS), TDES0[29], in the descriptor is set and Timestamp status (TTSS) bit, TDES0[17], is set.