15.7.25 EPHYBICSR1 Register (Address = 0x1B) [reset = 0x7D]
Ethernet PHY BIST Control and Status 1 - MR27 (EPHYBICSR1)
This register provides the total number of error bytes that are received by the PRBS checker and defines the Inter-Packet Gap (IPG) for the packet generator.
EPHYBICSR1 is shown in Figure 15-113 and described in Table 15-125.
Return to Summary Table.
Figure 15-113 EPHYBICSR1 Register
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| ERRCNT |
IPGLENGTH |
| R-0x0 |
R/W-0x7D |
|
Table 15-125 EPHYBICSR1 Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 15-8 |
ERRCNT |
R |
0x0 |
BIST Error Count. This field holds the number of erroneous bytes that were received by the PRBS checker. The value in this register is locked when a write is done to bit 15. When the PRBSM field in the EPHYBISCR register (0x0016) is set to zero, the count stops at 0xFF. See the EPHYBISCR register for further details.
|
| 7-0 |
IPGLENGTH |
R/W |
0x7D |
BIST IPG Length. Inter Packet Gap (IPG) Length defines the size of the gap (in bytes) between any 2 successive packets generated by the BIST. Default value is 0x7D, which is equal to 125 bytes.
|