| 15 |
MIIRESET |
R/W |
0x0 |
MII Register reset. Writing a 1 to this bit resets the contents of the MII-related registers: EPHYBMCR (0x000) EPHYANA (0x004) and EPHYANNPTR (0x007). When the reset operation is done, this bit is cleared to 0 automatically.
0x0 = Normal operation.
0x1 = Initiate MII Reset / Reset in Process.
|
| 14 |
MIILOOPBK |
R/W |
0x0 |
MII Loopback. When MII loopback mode is activated, the transmitter data presented on MII TXD is looped back to MII RXD internally.
0x0 = Normal operation.
0x1 = MII Loopback enabled.
|
| 13 |
SPEED |
R/W |
0x1 |
Speed Select. When auto-negotiation is disabled writing to this bit allows the port speed to be selected.
0x0 = 10Mbs
0x1 = 100Mbs
|
| 12 |
ANEN |
R/W |
0x1 |
Auto-Negotiate Enable.
0x0 = Auto-Negotiation Disabled. The SPEED bit and the DUPLEXM bit determine the port speed and duplex mode.
0x1 = Auto-Negotiation Enabled. The SPEED bit and the DUPLEXM bit of this register are ignored when this bit is set.
|
| 11 |
PWRDWN |
R/W |
0x0 |
Power Down. Setting this bit powers down the PHY. Only minimal register functionality is enabled during the power down condition.
0x0 = Normal operation
0x1 = Power-down modes are enabled: General Power Down Mode, Active Sleep Mode and Passive Sleep Mode (see Ethernet PHY Specific Control (EPHYSCR) register, offset 0x011.
|
| 10 |
ISOLATE |
R/W |
0x0 |
Port Isolate.
0x0 = Normal operation.
0x1 = Isolates the Port from the MII with the exception of the serial management.
|
| 9 |
RESTARTAN |
R/W |
0x0 |
Restart Auto-Negotiation.
0x0 = Normal operation.
0x1 = Auto-Negotiation process is re-initiated. If Auto-Negotiation is disabled (ANEN = 0), this bit is ignored. This bit is self-clearing and returns a value of 1 until Auto-Negotiation is initiated, whereupon it self-clears. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit.
|
| 8 |
DUPLEXM |
R/W |
0x1 |
Duplex Mode. When auto-negotiation is disabled writing to this bit allows the port-duplex capability to be selected.
0x0 = Half Duplex operation.
0x1 = Full Duplex Operation
|
| 7 |
COLLTST |
R/W |
0x0 |
Collision Test. When set, this bit causes the EN0COL signal to be asserted in response to the assertion of EN0TXEN within 512 bit times. The EN0COL signal is deasserted within four bit times in response to the deassertion of EN0TXEN.
0x0 = Normal operation
0x1 = Collision test enabled.
|
| 6-0 |
RESERVED |
R |
0x0 |
|