15.7.11 EPHYCFG2 Register (Address = 0xA) [reset = 0x4]
Ethernet PHY Configuration 2 - MR10 (EPHYCFG2)
Fields in this register are used to configure the Ethernet PHY. These configuration values are programmed by the system processor after a POR. The DONE bit in the EPHYCFG1 register is set when configuration is complete. This register is used when the user requires a configuration different from what is provided in the EMACPC register.
EPHYCFG2 is shown in Figure 15-99 and described in Table 15-111.
Return to Summary Table.
Figure 15-99 EPHYCFG2 Register
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
FLUPPD |
EXTFD |
ENLEDLINK |
ISOMIILL |
RXERRIDLE |
ODDNDETDIS |
RESERVED |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x1 |
R/W-0x0 |
R-0x0 |
|
Table 15-111 EPHYCFG2 Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 15-7 |
RESERVED |
R |
0x0 |
|
| 6 |
FLUPPD |
R/W |
0x0 |
Fast Link-Up in Parallel Detect Mode. In fast-auto MDI-X and in robust-auto MDI-X modes (bits 6 and 5 in register EPHYCFG1), this bit is automatically set.
0x0 = Normal Parallel Detection link establishment
0x1 = Enable Fast Link-Up time During Parallel Detection
|
| 5 |
EXTFD |
R/W |
0x0 |
Extended Full-Duplex Ability. Encodes the type of PHY attached.
0x0 = Disable extended full-duplex ability. Decision to work in full-duplex or half-duplex mode follows IEEE specification.
0x1 = Force full-duplex while working with link partner in forced 100B-TX. When the PHY is set to Auto-Negotiation or Force 100B-TX and the link partner is operated in Force 100B-TX, the link is always full duplex
|
| 4 |
ENLEDLINK |
R/W |
0x0 |
Enhanced LED Functionality.
0x0 = LED Link is ON when link is established.
0x1 = LED Link is ON only when link is established in 100B-TX Full Duplex mode.
|
| 3 |
ISOMIILL |
R/W |
0x0 |
Isolate MII outputs when Enhanced Link is not Achievable.
0x0 = Normal MII outputs operation
0x1 = When no link established in 100B-TX and Full Duplex conditions, MII outputs are tied low.
|
| 2 |
RXERRIDLE |
R/W |
0x1 |
Detection of Receive Symbol Error During IDLE State.
0x0 = Disable detection of Receive symbol error during IDLE state.
0x1 = Enable detection of Receive symbol error during IDLE state.
|
| 1 |
ODDNDETDIS |
R/W |
0x0 |
Detection of Transmit Error.
0x0 = Enable detection of deassertion of the internal transmit enable on an odd-nibble boundary. In this case the internal transmit enable is extended by one additional transmit clock cycle and behaves as if the internal transmit error was asserted during that additional cycle.
0x1 = Disable detection of internal transmit error in odd-nibble boundary.
|
| 0 |
RESERVED |
R |
0x0 |
|