SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Ethernet PHY Masked Interrupt Status and Clear (EPHYMISC)
The Ethernet Masked Interrupt Status and Clear (EPHYMISC) register displays the masked interrupt status of the Ethernet PHY, which is either from the internal integrated PHY or an external PHY. This register can be written to clear the EPHYRIS register.
This register is used for clearing the EPHYRIS register bits.
EPHYMISC is shown in Figure 15-88 and described in Table 15-98.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0x0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT | ||||||||||||||
R-0x0 | R/W1C-0x0 | ||||||||||||||