15.7.28 EPHYRCR Register (Address = 0x1F) [reset = 0x0]
Ethernet PHY Reset Control - MR31 (EPHYRCR)
This register allows the system to reset or restart the PHY by register access.
EPHYRCR is shown in Figure 15-116 and described in Table 15-128.
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Figure 15-116 EPHYRCR Register
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| SWRST |
SWRESTART |
RESERVED |
| R/W-0x0 |
R/W-0x0 |
R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
| R-0x0 |
|
Table 15-128 EPHYRCR Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 15 |
SWRST |
R/W |
0x0 |
Software Reset.
0x0 = Normal Operation.
0x1 = Soft reset. This mode resets the digital portion of the PHY and all of the registers. This bit self clears after completion.
|
| 14 |
SWRESTART |
R/W |
0x0 |
Software Restart.
0x0 = Normal Operation.
0x1 = Restart PHY. This mode resets the digital portion of the PHY but no the registers. This bit self clears after completion of the restart.
|
| 13-0 |
RESERVED |
R |
0x0 |
|