15.7.13 EPHYREGCTL Register (Address = 0xD) [reset = 0x0]
Ethernet PHY Register Control - MR13 (EPHYREGCTL)
EPHYREGCTL (0x00D) and EPHYADDAR (0x00E) registers allow read and write access to the extended register set using indirect addressing. The modes for the FUNC field are as follows:
- EPHYREGCTL[15:14] = 0x0: A write to EPHYADDAR modifies the extended register set address register. This address register must be initialized in order to access any of the registers within the extended register set.
- EPHYREGCTL[15:14] = 0x1: A read/write to EPHYADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. The address register contents (pointer) remain unchanged.
- EPHYREGCTL[15:14] = 0x2: A read/write to EPHYADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. After that access is complete, for both reads and writes, the value in the address register is incremented.
- EPHYREGCTL[15:14] = 0x3: A read/write to EPHYADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. After that access is complete, for write accesses only, the value in the address register is incremented. For read accesses, the value of the address register remains unchanged.
This register is the MDIO Manageable Device (MMD) access control. In general, register EPHYREGCTL [4:0] is the device address, DEVAD, that directs any accesses of EPHYADDAR (0x00E) register to the appropriate MMD. It also contains selection bits for auto-increment of the data register. This register contains the device address to be written to access the extended registers. Write 0x1F into bits [4:0] of this register. It also contains selection bits [15:14] for the address auto-increment mode of EPHYADDAR.
EPHYREGCTL is shown in Figure 15-101 and described in Table 15-113.
Return to Summary Table.
Figure 15-101 EPHYREGCTL Register
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| FUNC |
RESERVED |
DEVAD |
| W-0x0 |
R-0x0 |
W-0x0 |
|
Table 15-113 EPHYREGCTL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 15-14 |
FUNC |
W |
0x0 |
Function.
0x0 = Address
0x1 = Data, no post increment
0x2 = Data, post increment on read and write
0x3 = Data, post increment on write only
|
| 13-5 |
RESERVED |
R |
0x0 |
|
| 4-0 |
DEVAD |
W |
0x0 |
Device Address. In general, these bits [4:0] are the device address DEVAD that directs any accesses of EPHYADDAR register (0x00E) to the appropriate MMD. The PHY uses the vendor specific DEVAD [4:0] = 0x1F for accesses. All accesses through registers EPHYREGCR and EPHYADDAR should use this DEVAD. Transactions with other DEVAD are ignored.
|