MDI-X Mode. This is a read-only status as reported by the Auto-Negation state machine: This bit is affected by the settings of the MDIXEN and FORCEMDIX bits in the EPHYCTL register. When MDIX is enabled, but not forced, this bit updates dynamically as the Auto-MDIX algorithm swaps between MDI and MDI-X configurations.

0x0 = MDI pairs normal (Receive on TPRD pair, Transmit on TPTD pair)

0x1 = MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair)

Receive Error Latch. This bit is cleared on a read of the EPHYRXERCNT register.

0x0 = No receive error event has occurred.

0x1 = Receive error event has occurred since last read of EPHYRXERCNT register (PHY offset 0x015).

Polarity Status. This bit is a duplication of bit 4 (POLSTAT) in the EPHY10BTSC register (PHY offset 0x01A). This bit is cleared upon a read of the EPHY10BTSC register, but not on a read of the EPHYSTS register.

0x0 = Correct Polarity detected.

0x1 = Inverted Polarity detected.

False Carrier Sense Latch. This bit is cleared on a read of the EPHYFCSR register.

0x0 = No False Carrier event has occurred.

0x1 = False Carrier event has occurred since last read of EPHYFCSCR register (0x014).

Signal Detect. This bit displays the active high 100Base-TX unconditional Signal Detect indication from the PMD (Physical Layer Medium Dependent). This bit is latched low and held until it is read, based upon the occurrence of the corresponding event.

Descrambler Lock. This bit displays the active high 100Base-TX Descrambler Lock indication from PMD. This bit is latched low and held until it is read, based upon the occurrence of the corresponding event.

Link Code Page Received. This bit is not cleared upon a read of the EPHYSTS register.

0x0 = Link Code Word Page has not been received.

0x1 = A new Link Code Word Page has been received. This is a duplicate of Page Received (bit 1) in the EPHYANER register and it is cleared on read of the EPHYANER register (0x006).

MII Interrupt Pending.

0x0 = No interrupt pending

0x1 = Indicates that an internal interrupt is pending. Interrupt source can be determined by reading the EPHYMISR1 Register (PHY offset 0x012). Reading the EPHYMISR1 clears this Interrupt bit indication.

Remote Fault.

0x0 = No remote fault condition detected.

0x1 = Remote Fault condition detected. Criteria for a fault is when there is notification from Link Partner of Remote Fault via Auto-Negotiation. Cleared on read of EPHYBMSR register (PHY offset 0x001) or by reset.

Jabber Detect. This bit will not be cleared upon a read of the EPHYSTS register.

0x0 = No Jabber.

0x1 = Jabber condition detected. This bit has meaning only in 10 Mb/s mode. This bit is a duplicate of the Jabber Detect bit in the EPHYBMSR register (PHY offset 0x001).

Auto-Negotiation Status.

0x0 = Auto-Negotiation not complete.

0x1 = Auto-Negotiation complete.

MII Loopback Status.

0x0 = Normal operation.

0x1 = Loopback active (enabled).

Duplex Status. This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes. Therefore, it is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link.

0x0 = Half Duplex Mode

0x1 = Full Duplex Mode

Speed Status. This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced Modes. It is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link.

0x0 = 100 Mb/s mode.

0x1 = 10 Mb/s mode.

Link Status. This bit is not cleared upon a read of the EPHYSTS register.

0x0 = Link is not established.

0x1 = Valid link is established (for either 10 or 100 Mb/s operation). This bit is a duplicate of the Link Status bit in the EPHYBMSR register (PHY offset 0x001).