SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
If the RX FIFO is full before it receives the EOF data from the MAC, an overflow is declared, the entire frame (including the status word) is dropped and the Ethernet MAC Missed Frame and Buffer Overflow Counter (EMACMFBOC) register is incremented. These error actions occur even if the FEF bit is set in the EMACDMAPOPMODE register. If the start address of such a frame has already been transferred to the TX/RX Controller, the rest of the frame is dropped and a dummy EOF is written to the FIFO along with its status word. The descriptor status indicates a partial frame because of overflow. In such frames, the Frame Length (FL) field in the receive descriptor is invalid. If the RX FIFO is configured to operate in the store-and-forward mode and if the length of the received frame is more than the FIFO size, overflow occurs and all such frames are dropped. During error handling, the DMA flushes the error frame currently being read.
The Receive control logic can filter error and undersized frames if enabled through configuring the FEF or FUF bit of the EMACDMAOPMODE register. Filtering must be set before the start address of the frame has been transferred to the TX/RX controller for it to take effect.