SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Available clock sources are dependent on the interface chosen. The following sections describe the clock control for the various interfaces.
The Ethernet Controller module and integrated PHY receive two clock inputs. A gated system clock acts as the clock source to the CSRs of the Ethernet MAC and must be 20 MHz or greater for correct operation. The SYSCLK frequency for run, sleep, and deep-sleep modes is programmed in the System Control module. See Section 15.3.1 for more information.