SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
After reset, when the EMAC is powered and enabled, the EMACPC register default reset value may be sampled and used to configure the PHY. The results of this configuration can also be read in the following EPHY registers:
The mappings of the EMACPC register bits to the PHY register and bits are as follows:
| EMACPC Register Bit | Corresponding PHY Register | Corresponding PHY Bit (Bit No.) |
|---|---|---|
| PHYEXT | N/A | N/A |
| DIGRESTART | N/A | N/A |
| NIBDETDIS | EPHYCFG2 | ODDNDETDIS (1) |
| RXERIDLE | EPHYCFG2 | RXERRIDLE (2) |
| ISOMILL | EPHYCFG2 | ISOMILL (3) |
| LRR | EPHYCFG1 | LLR (7) |
| TDRRUN | EPHYCFG1 | TDRAR (8) |
| FASTLDMODE | EPHYCFG3 | FLDWNM (4:0) |
| POLSWAP | EPHYCFG3 | POLSWAP (7) |
| MDISWAP | EPHYCFG3 | MDIMDIXS (6) |
| RBSTMDIX | EPHYCFG1 | RAMDIX (5) |
| FASTMDIX | EPHYCFG1 | FAMDIX (6) |
| MDIXEN | EPHYCTL | AUTOMDI (15) |
| FASTRXDV | EPHYCFG1 | FRXDVDET (1) |
| FASTLUPD | EPHYCFG2 | FLUPPD (6) |
| EXTFD | EPHYCFG2 | EXTFD (5) |
| FASTANEN | EPHYCFG1 | FASTANEN (4) |
| FASTANSEL | EPHYCFG1 | FANSEL (3:2) |
| ANEN | EPHYBMCR | ANEN |
| ANMODE | N/A | N/A |
| PHYHOLD | N/A | N/A |
The MAC module and registers are enabled and powered at reset. When reset has completed and the clock to the Ethernet MAC is enabled by setting the R0 bit in the Ethernet Controller Run Mode Clock Gating Control (RCGCEMAC) register at System Control Module offset 0x69C, the application has the option to enable the PHY with its default interface configuration (as defined by the Ethernet MAC Peripheral Configuration Register (EMACPC) register) or with a custom configuration.