SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The Arm Cortex-M4F processor and the NVIC prioritize and handle all exceptions in handler mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the ISR. The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, which enables performance of back-to-back interrupts to be performed without the overhead of state saving and restoration.
Table 1-19 lists all exception types. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on interrupts (see Table 1-19).
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn) registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting priority levels into preemption priorities and subpriorities. All the interrupt registers are described in Section 2.2.2.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset, Nonmaskable Interrupt (NMI), and a Hard Fault, in that order. The default priority is 0 for all the programmable priorities.
NOTE
After a write to clear an interrupt source, several processor cycles may be needed for the NVIC to identify the interrupt source deassert. Thus if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the NVIC sees the interrupt as still asserted, causing errant re-entry of the interrupt handler. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer).
See Section 2.2.2 for more information on exceptions and interrupts.