| 31-26 |
RESERVED |
R |
0x0 |
|
| 25 |
DIV0 |
R/W1C |
0x0 |
Divide-by-Zero Usage Fault
When this bit is set, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Trapping on divide-by-zero is enabled by setting the DIV0 bit in the Configuration and Control (CFGCTRL) register (see ). This bit is cleared by writing a 1 to it.
|
| 24 |
UNALIGN |
R/W1C |
0x0 |
Unaligned Access Usage Fault
Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the configuration of this bit. Trapping on unaligned access is enabled by setting the UNALIGNED bit in the CFGCTRL register (see ). This bit is cleared by writing a 1 to it.
|
| 23-20 |
RESERVED |
R |
0x0 |
|
| 19 |
NOCP |
R/W1C |
0x0 |
No Coprocessor Usage Fault
This bit is cleared by writing a 1 to it.
|
| 18 |
INVPC |
R/W1C |
0x0 |
Invalid PC Load Usage Fault
When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing a 1 to it.
|
| 17 |
INVSTAT |
R/W1C |
0x0 |
Invalid State Usage Fault
When this bit is set, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the Execution Program Status Register (EPSR) register. This bit is not set if an undefined instruction uses the EPSR register. This bit is cleared by writing a 1 to it.
|
| 16 |
UNDEF |
R/W1C |
0x0 |
Undefined Instruction Usage Fault
When this bit is set, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. This bit is cleared by writing a 1 to it.
|
| 15 |
BFARV |
R/W1C |
0x0 |
Bus Fault Address Register Valid
This bit is set after a bus fault, where the address is known. Other faults can clear this bit, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active bus fault handler whose FAULTADDR register value has been overwritten. This bit is cleared by writing a 1 to it.
|
| 14 |
RESERVED |
R |
0x0 |
|
| 13 |
BLSPERR |
R/W1C |
0x0 |
Bus Fault on Floating-Point Lazy State Preservation
This bit is cleared by writing a 1 to it.
|
| 12 |
BSTKE |
R/W1C |
0x0 |
Stack Bus Fault
When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it.
|
| 11 |
BUSTKE |
R/W1C |
0x0 |
Unstack Bus Fault
This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it.
|
| 10 |
IMPRE |
R/W1C |
0x0 |
Imprecise Data Bus Error
When this bit is set, a fault address is not written to the FAULTADDR register. This fault is asynchronous. Therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both the IMPRE bit is set and one of the precise fault status bits is set. This bit is cleared by writing a 1 to it.
|
| 9 |
PRECISE |
R/W1C |
0x0 |
Precise Data Bus Error
When this bit is set, the fault address is written to the FAULTADDR register. This bit is cleared by writing a 1 to it.
|
| 8 |
IBUS |
R/W1C |
0x0 |
Instruction Bus Error
The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it.
|
| 7 |
MMARV |
R/W1C |
0x0 |
Memory Management Fault Address Register Valid
If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active memory management fault handler whose MMADDR register value has been overwritten. This bit is cleared by writing a 1 to it.
|
| 6 |
RESERVED |
R |
0x0 |
|
| 5 |
MLSPERR |
R/W1C |
0x0 |
Memory Management Fault on Floating-Point Lazy State Preservation
This bit is cleared by writing a 1 to it.
|
| 4 |
MSTKE |
R/W1C |
0x0 |
Stack Access Violation
When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it.
|
| 3 |
MUSTKE |
R/W1C |
0x0 |
Unstack Access Violation
This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it.
|
| 2 |
RESERVED |
R |
0x0 |
|
| 1 |
DERR |
R/W1C |
0x0 |
Data Access Violation
When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is written to the MMADDR register. This bit is cleared by writing a 1 to it.
|
| 0 |
IERR |
R/W1C |
0x0 |
Instruction Access Violation
This fault occurs on any access to an XN region, even when the MPU is disabled or not present. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing a 1 to it.
|