SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
During sleep or deep-sleep mode, flash memory can be in either the default active mode or the low-power mode, while SRAM can be in the default active mode, standby mode, or low-power mode. The active mode in each case provides the fastest times to sleep and wake up, but consumes more power. Low-power mode provides the lowest power consumption, but the device takes longer to sleep and wake up.
The SRAM can be programmed to prohibit any power management by configuring the SRAMPM bit in the Sleep Power Configuration (SLPPWRCFG) register. This configuration provides the fastest sleep and wake-up times but consumes the most power while in sleep and deep-sleep modes.
The following power saving options are available in sleep and deep-sleep modes:
The SDPMST register provides results on the dynamic power management command issued. The SDPMST register also reports some real-time status that can be viewed by a debugger or by the core if it is running. These events do not trigger an interrupt and are meant to provide information to help tune software for power management. The status register is written at the beginning of every dynamic power management event request that provides error checking. There is no mechanism to clear the bits; they are overwritten on the next event. The data is real time, and no event registers that information.