SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The flash memory is configured in groups of four banks of 16K × 128 bits (4 × 256KB total) that are two-way interleaved (see Figure 7-3).
The interleaved memory prefetches 256 bits at a time. The prefetch buffers allow the maximum performance of a 120-MHz CPU speed to be maintained with linear code or loops that fit within the prefetch buffer. It is recommended that code be compiled with switches set to eliminate literals as much as possible, as a literal causes a flash access for that word and a stall for the wait states. Most compilers support transforming literals into in-line code, which executes faster in a system in which the memory subsystem is slower than the CPU.
Because the memory is two-way interleaved and each bank individually is an 8KB sector, when the user erases a sector, using the ERASE bits in the Flash Memory Control (FMC) register, it is a 16KB erase. Erasing a block causes the entire contents of the block to be reset to all 1s.