7.3.13 FLASHCONF Register (Offset = 0xFC8) [reset = 0x0]
Flash Configuration Register (FLASHCONF)
The FLASHCONF register allows the user to enable or disable various properties of the Flash. The force bits, FBFON and FBFOFF, can be used to test code performance and execution by turning the prefetch buffers on and subsequently forcing them off.
FLASHCONF is shown in Figure 7-21 and described in Table 7-20.
Return to Summary Table.
Figure 7-21 FLASHCONF Register
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
RESERVED |
FMME |
SPFE |
RESERVED |
R-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
|
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
RESERVED |
CLRTV |
RESERVED |
FPFON |
FPFOFF |
R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
R/W-0x0 |
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
RESERVED |
R-0x0 |
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
R-0x0 |
|
Table 7-20 FLASHCONF Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
31 |
RESERVED |
R |
0x0 |
|
30 |
FMME |
R/W |
0x0 |
Flash Mirror Mode Enable
0x0 = Flash mirror mode is disabled.
0x1 = Flash mirror mode feature is enabled. Access to the lower banks is translated to upper.
|
29 |
SPFE |
R/W |
0x0 |
Single Prefetch Mode Enable
0x0 = A 4x256-bit prefetch buffer is enabled and used.
0x1 = A single 2x256-bit prefetch buffer is enabled and used.
|
28-21 |
RESERVED |
R |
0x0 |
|
20 |
CLRTV |
R/W |
0x0 |
Clear Valid Tags This is a self-clearing bit.
0x0 = No effect.
0x1 = Clear valid tags in the prefetch buffer.
|
19-18 |
RESERVED |
R |
0x0 |
|
17 |
FPFON |
R/W |
0x0 |
Force Prefetch On
0x0 = No effect
0x1 = Force prefetch buffers to be enabled.
|
16 |
FPFOFF |
R/W |
0x0 |
Force Prefetch Off
0x0 = No effect
0x1 = Force prefetch buffers to be disabled.
|
15-0 |
RESERVED |
R |
0x0 |
|