SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The Ethernet MAC can control the following features of the EN0PPS output:
The start time can be programmed in the EMACTARGSEC and EMACTARGNANO registers. The TRGTBUSY bit in the EMACTARGNANO register indicates when the value is synchronized to the PTP clock domain. When this bit is clear, a new start time can be programmed, even before the earlier start time has elapsed. The start or stop time should be programmed with advanced system time to ensure proper EN0PPS signal output. If the application programs a start or stop time that has already elapsed, then the MAC sets an error status bit indicating the programming error. If enabled, the MAC also sets the Target Time Reached interrupt event. The application can cancel the start or stop request only if the corresponding start or stop time has not elapsed. If the time has elapsed, the cancel command has no effect.
For a flexible EN0PPS output, the EMACPPS0INTVL and EMACPPS0WIDTH registers can be configured. The PPS0WIDTH and PPS0INT fields are programmed in terms of granularity of system time, that is, number of the units of subsecond increment value. For example, to have a EN0PPS pulse width of 80 ns and interval of 120ns, with the PTP reference clock of 25MHz, you should program the width and interval to values 1 and 2, respectively. Note that the PPS0WIDTH and PPS0INT value must be programmed as one less than the required interval. Before giving the command to trigger a pulse or pulse train on the EN0PPS output, the interval and width of the PPS signal output should be programmed or updated.