SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Each data frame is between 4 and 16 bits long in legacy mode and 8-bits in advanced, bi-, and quad-SSI mode and is transmitted starting with the MSB. There are two basic frame types that can be selected by programming the FRF bit in the SSICR0 register:
NOTE
Advanced, Bi- and Quad-SSI modules only supports Freescale mode when SPH = 0, SPO = 0, and DDS = 0x8 in the SSI Control 0 (SSICR0) register.
For both formats, the serial clock (SSInClk) is held inactive while the QSSI is idle, and SSInClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSInClk is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period.
For Freescale SPI frame format, the serial frame (SSInFss) pin is active low, and is asserted (pulled down) during the entire transmission of the frame.
For TI synchronous serial frame format, the SSInFss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the QSSI and the off-chip slave device drive their output data on the rising edge of SSInClk and latch data from the other device on the falling edge.
Table 23-3 is a synopsis of the features supported in each frame format when operating in legacy Mode:
| Feature | TI Mode | Freescale SPI Mode |
|---|---|---|
| Frame hold | Not available | Available |
| High speed (master RX only) | Not available | Available |
| SPO and SPH configuration | Not available | Available and can be used in combination with frame hold and high-speed mode |
| Frequency (system clock: SSInCLK) | Master 1:2
Slave 1:12 |
Master 1:2
Slave 1:12 |
For advanced, bi-, and quad-SSI modes using the Freescale SPI format or the bi- and quad-SSI modes using the TI format, the following features are supported: